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Difference between revisions of "intel/xeon silver/4110"
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{{intel title|Xeon Silver 4110}} | {{intel title|Xeon Silver 4110}} | ||
− | {{ | + | {{chip |
|name=Xeon Silver 4110 | |name=Xeon Silver 4110 | ||
|image=skylake sp (basic).png | |image=skylake sp (basic).png | ||
Line 9: | Line 9: | ||
|part number 2=CD8067303561400 | |part number 2=CD8067303561400 | ||
|s-spec=SR3GH | |s-spec=SR3GH | ||
+ | |s-spec qs=QN09 | ||
|market=Server | |market=Server | ||
|first announced=July 11, 2017 | |first announced=July 11, 2017 | ||
Line 19: | Line 20: | ||
|turbo frequency1=3,000 MHz | |turbo frequency1=3,000 MHz | ||
|clock multiplier=21 | |clock multiplier=21 | ||
+ | |cpuid=0x50654 | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
− | |microarch=Skylake | + | |microarch=Skylake (server) |
|platform=Purley | |platform=Purley | ||
|chipset=Lewisburg | |chipset=Lewisburg | ||
Line 32: | Line 34: | ||
|core count=8 | |core count=8 | ||
|thread count=16 | |thread count=16 | ||
+ | |max memory=768 GiB | ||
|max cpus=2 | |max cpus=2 | ||
− | | | + | |smp interconnect=UPI |
+ | |smp interconnect links=2 | ||
+ | |smp interconnect rate=9.6 GT/s | ||
|tdp=85 W | |tdp=85 W | ||
|tcase min=0 °C | |tcase min=0 °C | ||
|tcase max=77 °C | |tcase max=77 °C | ||
− | |package | + | |dts min=0 °C |
+ | |dts max=90 °C | ||
+ | |package name 1=intel,fclga_3647 | ||
+ | |successor=Xeon Silver 4210 | ||
+ | |successor link=intel/xeon_silver/4210 | ||
}} | }} | ||
− | '''Xeon Silver 4110''' is a {{arch|64}} [[octa-core]] [[x86]] dual-socket mid-range performance server microprocessor introduced by [[Intel]] in mid-2017. The Silver 4110, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 85 W and a {{intel|turbo boost}} frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory. | + | '''Xeon Silver 4110''' is a {{arch|64}} [[octa-core]] [[x86]] dual-socket mid-range performance server microprocessor introduced by [[Intel]] in mid-2017. The Silver 4110, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 85 W and a {{intel|turbo boost}} frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory. |
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} |
{{cache size | {{cache size | ||
|l1 cache=512 KiB | |l1 cache=512 KiB | ||
Line 175: | Line 184: | ||
|xfr=No | |xfr=No | ||
}} | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=2,100 MHz | ||
+ | |freq_1=3,000 MHz | ||
+ | |freq_2=3,000 MHz | ||
+ | |freq_3=2,800 MHz | ||
+ | |freq_4=2,800 MHz | ||
+ | |freq_5=2,400 MHz | ||
+ | |freq_6=2,400 MHz | ||
+ | |freq_7=2,400 MHz | ||
+ | |freq_8=2,400 MHz | ||
+ | |freq_avx2_base=1,700 MHz | ||
+ | |freq_avx2_1=2,900 MHz | ||
+ | |freq_avx2_2=2,900 MHz | ||
+ | |freq_avx2_3=2,700 MHz | ||
+ | |freq_avx2_4=2,700 MHz | ||
+ | |freq_avx2_5=2,100 MHz | ||
+ | |freq_avx2_6=2,100 MHz | ||
+ | |freq_avx2_7=2,100 MHz | ||
+ | |freq_avx2_8=2,100 MHz | ||
+ | |freq_avx512_base=1,000 MHz | ||
+ | |freq_avx512_1=1,800 MHz | ||
+ | |freq_avx512_2=1,800 MHz | ||
+ | |freq_avx512_3=1,600 MHz | ||
+ | |freq_avx512_4=1,600 MHz | ||
+ | |freq_avx512_5=1,300 MHz | ||
+ | |freq_avx512_6=1,300 MHz | ||
+ | |freq_avx512_7=1,300 MHz | ||
+ | |freq_avx512_8=1,300 MHz | ||
+ | }} | ||
+ | |||
+ | [[Category:microprocessor models by intel based on skylake low core count die]] |
Latest revision as of 12:16, 29 December 2019
Edit Values | |
Xeon Silver 4110 | |
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General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 4110 |
Part Number | BX806734110, CD8067303561400 |
S-Spec | SR3GH QN09 (QS) |
Market | Server |
Introduction | July 11, 2017 (announced) July 11, 2017 (launched) |
Release Price | $501.00 |
Shop | Amazon |
General Specs | |
Family | Xeon Silver |
Series | 4000 |
Locked | Yes |
Frequency | 2,100 MHz |
Turbo Frequency | 3,000 MHz (1 core) |
Clock multiplier | 21 |
CPUID | 0x50654 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | U0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 16 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 2 |
Interconnect Rate | 9.6 GT/s |
Electrical | |
TDP | 85 W |
Tcase | 0 °C – 77 °C |
TDTS | 0 °C – 90 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Xeon Silver 4110 is a 64-bit octa-core x86 dual-socket mid-range performance server microprocessor introduced by Intel in mid-2017. The Silver 4110, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm process, sports 1 AVX-512 FMA unit as well as two Ultra Path Interconnect links. This microprocessor, which operates at 2.1 GHz with a TDP of 85 W and a turbo boost frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.
Cache[edit]
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||
---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | ||
Normal | 2,100 MHz | 3,000 MHz | 3,000 MHz | 2,800 MHz | 2,800 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz |
AVX2 | 1,700 MHz | 2,900 MHz | 2,900 MHz | 2,700 MHz | 2,700 MHz | 2,100 MHz | 2,100 MHz | 2,100 MHz | 2,100 MHz |
AVX512 | 1,000 MHz | 1,800 MHz | 1,800 MHz | 1,600 MHz | 1,600 MHz | 1,300 MHz | 1,300 MHz | 1,300 MHz | 1,300 MHz |
Facts about "Xeon Silver 4110 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Silver 4110 - Intel#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
supported memory type | DDR4-2400 + |