From WikiChip
Difference between revisions of "intel/xeon silver/4112"
(Created page with "{{intel title|Xeon Silver 4112}} {{mpu}}") |
|||
(23 intermediate revisions by 4 users not shown) | |||
Line 1: | Line 1: | ||
{{intel title|Xeon Silver 4112}} | {{intel title|Xeon Silver 4112}} | ||
− | {{ | + | {{chip |
+ | |name=Xeon Silver 4112 | ||
+ | |image=skylake sp (basic).png | ||
+ | |designer=Intel | ||
+ | |manufacturer=Intel | ||
+ | |model number=4112 | ||
+ | |part number=BX806734112 | ||
+ | |part number 2=CD8067303562100 | ||
+ | |s-spec=SR3GN | ||
+ | |s-spec qs=QN0E | ||
+ | |market=Server | ||
+ | |first announced=July 11, 2017 | ||
+ | |first launched=July 11, 2017 | ||
+ | |release price=$473.00 | ||
+ | |family=Xeon Silver | ||
+ | |series=4000 | ||
+ | |locked=Yes | ||
+ | |frequency=2,600 MHz | ||
+ | |turbo frequency1=3,000 MHz | ||
+ | |clock multiplier=26 | ||
+ | |cpuid=0x50654 | ||
+ | |isa=x86-64 | ||
+ | |isa family=x86 | ||
+ | |microarch=Skylake (server) | ||
+ | |platform=Purley | ||
+ | |chipset=Lewisburg | ||
+ | |core name=Skylake SP | ||
+ | |core family=6 | ||
+ | |core stepping=U0 | ||
+ | |process=14 nm | ||
+ | |technology=CMOS | ||
+ | |word size=64 bit | ||
+ | |core count=4 | ||
+ | |thread count=8 | ||
+ | |max memory=768 GiB | ||
+ | |max cpus=2 | ||
+ | |smp interconnect=UPI | ||
+ | |smp interconnect links=2 | ||
+ | |smp interconnect rate=9.6 GT/s | ||
+ | |tdp=85 W | ||
+ | |tcase min=0 °C | ||
+ | |tcase max=76 °C | ||
+ | |dts min=0 °C | ||
+ | |dts max=89 °C | ||
+ | |package name 1=intel,fclga_3647 | ||
+ | }} | ||
+ | '''Xeon Silver 4112''' is a {{arch|64}} [[quad-core]] [[x86]] dual-socket mid-range performance server microprocessor introduced by [[Intel]] in mid-2017. The Silver 4112, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.6 GHz with a TDP of 85 W and a {{intel|turbo boost}} frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} | ||
+ | The Xeon Silver 4112 features a considerably larger non-default 8.25 MiB of [[L3]], a size that would normally be found on a 6-core part. | ||
+ | {{cache size | ||
+ | |l1 cache=256 KiB | ||
+ | |l1i cache=128 KiB | ||
+ | |l1i break=4x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=128 KiB | ||
+ | |l1d break=4x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=4 MiB | ||
+ | |l2 break=4x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=8.25 MiB | ||
+ | |l3 break=6x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2400 | ||
+ | |ecc=Yes | ||
+ | |max mem=768 GiB | ||
+ | |controllers=2 | ||
+ | |channels=6 | ||
+ | |max bandwidth=107.3 GiB/s | ||
+ | |bandwidth schan=17.88 GiB/s | ||
+ | |bandwidth dchan=35.76 GiB/s | ||
+ | |bandwidth qchan=71.53 GiB/s | ||
+ | |bandwidth hchan=107.3 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 48 | ||
+ | | pcie config = x16 | ||
+ | | pcie config 2 = x8 | ||
+ | | pcie config 3 = x4 | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=Yes | ||
+ | |avx512cd=Yes | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=Yes | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=Yes | ||
+ | |intelnode=Yes | ||
+ | |kpt=Yes | ||
+ | |ptt=Yes | ||
+ | |mbe=Yes | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=No | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=2,600 MHz | ||
+ | |freq_1=3,000 MHz | ||
+ | |freq_2=3,000 MHz | ||
+ | |freq_3=2,900 MHz | ||
+ | |freq_4=2,900 MHz | ||
+ | |freq_avx2_base=2,200 MHz | ||
+ | |freq_avx2_1=2,900 MHz | ||
+ | |freq_avx2_2=2,900 MHz | ||
+ | |freq_avx2_3=2,600 MHz | ||
+ | |freq_avx2_4=2,600 MHz | ||
+ | |freq_avx512_base=1,100 MHz | ||
+ | |freq_avx512_1=1,800 MHz | ||
+ | |freq_avx512_2=1,800 MHz | ||
+ | |freq_avx512_3=1,400 MHz | ||
+ | |freq_avx512_4=1,400 MHz | ||
+ | }} | ||
+ | |||
+ | == Benchmarks == | ||
+ | {{benchmarks main | ||
+ | | | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00319.html|test_timestamp=2017-10-17 13:59:50-0400|chip_count=2|core_count=8|thread_count=8|vendor=HPE|system=ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Silver 4112)|SPECspeed2017_fp_base=41.4|SPECspeed2017_fp_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00347.html|test_timestamp=2017-10-23 20:49:08-0400|chip_count=2|core_count=8|copies_count=16|vendor=HPE|system=ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Silver 4112)|SPECrate2017_fp_base=51.8|SPECrate2017_fp_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00434.html|test_timestamp=2017-10-18 17:58:43-0400|chip_count=2|core_count=8|copies_count=16|vendor=HPE|system=ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Silver 4112)|SPECrate2017_int_base=44|SPECrate2017_int_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00445.html|test_timestamp=2017-10-24 15:29:40-0400|chip_count=2|core_count=8|thread_count=8|vendor=HPE|system=ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Silver 4112)|SPECspeed2017_fp_base=41.4|SPECspeed2017_fp_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00447.html|test_timestamp=2017-10-17 10:35:09-0400|chip_count=2|core_count=8|thread_count=8|vendor=HPE|system=ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Silver 4112)|SPECspeed2017_int_base=6.61|SPECspeed2017_int_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00453.html|test_timestamp=2017-10-23 16:05:38-0400|chip_count=2|core_count=8|copies_count=16|vendor=HPE|system=ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Silver 4112)|SPECrate2017_int_base=44.1|SPECrate2017_int_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00466.html|test_timestamp=2017-10-18 22:42:26-0400|chip_count=2|core_count=8|copies_count=16|vendor=HPE|system=ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Silver 4112)|SPECrate2017_fp_base=51.4|SPECrate2017_fp_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00469.html|test_timestamp=2017-10-24 12:05:11-0400|chip_count=2|core_count=8|thread_count=8|vendor=HPE|system=ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Silver 4112)|SPECspeed2017_int_base=6.63|SPECspeed2017_int_peak=}} | ||
+ | }} | ||
+ | |||
+ | [[Category:microprocessor models by intel based on skylake low core count die]] |
Latest revision as of 12:16, 29 December 2019
Edit Values | |
Xeon Silver 4112 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 4112 |
Part Number | BX806734112, CD8067303562100 |
S-Spec | SR3GN QN0E (QS) |
Market | Server |
Introduction | July 11, 2017 (announced) July 11, 2017 (launched) |
Release Price | $473.00 |
Shop | Amazon |
General Specs | |
Family | Xeon Silver |
Series | 4000 |
Locked | Yes |
Frequency | 2,600 MHz |
Turbo Frequency | 3,000 MHz (1 core) |
Clock multiplier | 26 |
CPUID | 0x50654 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | U0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 4 |
Threads | 8 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 2 |
Interconnect Rate | 9.6 GT/s |
Electrical | |
TDP | 85 W |
Tcase | 0 °C – 76 °C |
TDTS | 0 °C – 89 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Xeon Silver 4112 is a 64-bit quad-core x86 dual-socket mid-range performance server microprocessor introduced by Intel in mid-2017. The Silver 4112, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm process, sports 1 AVX-512 FMA unit as well as two Ultra Path Interconnect links. This microprocessor, which operates at 2.6 GHz with a TDP of 85 W and a turbo boost frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.
Cache[edit]
- Main article: Skylake § Cache
The Xeon Silver 4112 features a considerably larger non-default 8.25 MiB of L3, a size that would normally be found on a 6-core part.
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller[edit]
Integrated Memory Controller
|
||||||||||||||
|
Expansions[edit]
Expansion Options
|
||||||||
|
Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||
---|---|---|---|---|---|
1 | 2 | 3 | 4 | ||
Normal | 2,600 MHz | 3,000 MHz | 3,000 MHz | 2,900 MHz | 2,900 MHz |
AVX2 | 2,200 MHz | 2,900 MHz | 2,900 MHz | 2,600 MHz | 2,600 MHz |
AVX512 | 1,100 MHz | 1,800 MHz | 1,800 MHz | 1,400 MHz | 1,400 MHz |
Benchmarks[edit]
Test: SPEC CPU2017
Tested: 2017-10-17 13:59:50-0400
Chips: 2, Cores: 8, Threads: 8
Tested: 2017-10-17 13:59:50-0400
Chips: 2, Cores: 8, Threads: 8
Vendor: HPE
System: ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Silver 4112)
System: ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Silver 4112)
SPECspeed2017_fp_base: 41.4
Test: SPEC CPU2017
Tested: 2017-10-23 20:49:08-0400
Chips: 2, Cores: 8, Copies: 16
Tested: 2017-10-23 20:49:08-0400
Chips: 2, Cores: 8, Copies: 16
Vendor: HPE
System: ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Silver 4112)
System: ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Silver 4112)
SPECrate2017_fp_base: 51.8
Test: SPEC CPU2017
Tested: 2017-10-18 17:58:43-0400
Chips: 2, Cores: 8, Copies: 16
Tested: 2017-10-18 17:58:43-0400
Chips: 2, Cores: 8, Copies: 16
Vendor: HPE
System: ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Silver 4112)
System: ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Silver 4112)
SPECrate2017_int_base: 44
Test: SPEC CPU2017
Tested: 2017-10-24 15:29:40-0400
Chips: 2, Cores: 8, Threads: 8
Tested: 2017-10-24 15:29:40-0400
Chips: 2, Cores: 8, Threads: 8
Vendor: HPE
System: ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Silver 4112)
System: ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Silver 4112)
SPECspeed2017_fp_base: 41.4
Test: SPEC CPU2017
Tested: 2017-10-17 10:35:09-0400
Chips: 2, Cores: 8, Threads: 8
Tested: 2017-10-17 10:35:09-0400
Chips: 2, Cores: 8, Threads: 8
Vendor: HPE
System: ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Silver 4112)
System: ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Silver 4112)
SPECspeed2017_int_base: 6.61
Test: SPEC CPU2017
Tested: 2017-10-23 16:05:38-0400
Chips: 2, Cores: 8, Copies: 16
Tested: 2017-10-23 16:05:38-0400
Chips: 2, Cores: 8, Copies: 16
Vendor: HPE
System: ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Silver 4112)
System: ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Silver 4112)
SPECrate2017_int_base: 44.1
Test: SPEC CPU2017
Tested: 2017-10-18 22:42:26-0400
Chips: 2, Cores: 8, Copies: 16
Tested: 2017-10-18 22:42:26-0400
Chips: 2, Cores: 8, Copies: 16
Vendor: HPE
System: ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Silver 4112)
System: ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Silver 4112)
SPECrate2017_fp_base: 51.4
Test: SPEC CPU2017
Tested: 2017-10-24 12:05:11-0400
Chips: 2, Cores: 8, Threads: 8
Tested: 2017-10-24 12:05:11-0400
Chips: 2, Cores: 8, Threads: 8
Vendor: HPE
System: ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Silver 4112)
System: ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Silver 4112)
SPECspeed2017_int_base: 6.63
Facts about "Xeon Silver 4112 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Silver 4112 - Intel#io +, Xeon Silver 4112 - Intel +, Xeon Silver 4112 - Intel +, Xeon Silver 4112 - Intel +, Xeon Silver 4112 - Intel +, Xeon Silver 4112 - Intel +, Xeon Silver 4112 - Intel +, Xeon Silver 4112 - Intel + and Xeon Silver 4112 - Intel + |
base frequency | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
chipset | Lewisburg + |
clock multiplier | 26 + |
core count | 4 + |
core family | 6 + |
core name | Skylake SP + |
core stepping | U0 + |
cpuid | 0x50654 + |
designer | Intel + |
family | Xeon Silver + |
first announced | July 11, 2017 + |
first launched | July 11, 2017 + |
full page name | intel/xeon silver/4112 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 8.25 MiB (8,448 KiB, 8,650,752 B, 0.00806 GiB) + |
ldate | July 11, 2017 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 349.15 K (76 °C, 168.8 °F, 628.47 °R) + |
max cpu count | 2 + |
max dts temperature | 89 °C + |
max memory | 786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
microarchitecture | Skylake (server) + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min dts temperature | 0 °C + |
model number | 4112 + |
name | Xeon Silver 4112 + |
package | FCLGA-3647 + |
part number | BX806734112 + and CD8067303562100 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 473.00 (€ 425.70, £ 383.13, ¥ 48,875.09) + |
s-spec | SR3GN + |
s-spec (qs) | QN0E + |
series | 4000 + |
smp interconnect | UPI + |
smp interconnect links | 2 + |
smp interconnect rate | 9.6 GT/s + |
smp max ways | 2 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2400 + |
tdp | 85 W (85,000 mW, 0.114 hp, 0.085 kW) + |
technology | CMOS + |
thread count | 8 + |
turbo frequency (1 core) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |