Difference between revisions of "intel/xeon gold/6126t"

	Edit Values
	Xeon Gold 6126T
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	6126T
Part Number	CD8067303593100
S-Spec	SR3J9; QN39 (QS)
Market	Server
Introduction	April 25, 2017 (announced); July 11, 2017 (launched)
Release Price	$1865.00
Shop	Amazon
	General Specs
Family	Xeon Gold
Series	6100
Locked	Yes
Frequency	2,600 MHz
Turbo Frequency	3,700 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	26
CPUID	0x50654
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Skylake (server)
Platform	Purley
Chipset	Lewisburg
Core Name	Skylake SP
Core Family	6
Core Stepping	H0
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	12
Threads	24
Max Memory	768 GiB
	Multiprocessing
Max SMP	4-Way (Multiprocessor)
Interconnect	UPI
Interconnect Links	3
Interconnect Rate	10.4 GT/s
	Electrical
TDP	125 W
Tcase	0 °C – 74 °C
	Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647

Latest revision as of 00:20, 29 December 2019

Xeon Gold 6126T is a 64-bit dodeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6126T, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.6 GHz with a TDP of 125 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

This specific model (T) has 10 years extended life guarantees designed to be NEBS-friendly for use in NEBS-complaint applications.

Cache[edit]

Main article: Skylake § Cache

The Xeon Gold 6126T features a considerably larger non-default 19.25 MiB of L3, a size that would normally be found on a 14-core part.

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

768 KiB

786,432 B
0.75 MiB

L1I$	384 KiB 393,216 B 0.375 MiB	12x32 KiB	8-way set associative
L1D$	384 KiB 393,216 B 0.375 MiB	12x32 KiB	8-way set associative	write-back

L2$

12 MiB

12,288 KiB
12,582,912 B
0.0117 GiB

		12x1 MiB	16-way set associative	write-back

L3$

19.25 MiB

19,712 KiB
20,185,088 B
0.0188 GiB

		14x1.375 MiB	11-way set associative	write-back

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2666
Supports ECC	Yes
Max Mem	768 GiB
Controllers	2
Channels	6
Max Bandwidth	119.21 GiB/s 122,071.04 MiB/s 128.001 GB/s 128,000.763 MB/s 0.116 TiB/s 0.128 TB/s
Bandwidth	Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCIe

Revision	3.0
Max Lanes	48
Configs	x16, x8, x4

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
AVX-512	Advanced Vector 512-bit
AVX512F	AVX-512 Foundation
AVX512CD	AVX-512 Conflict Detection
AVX512BW	AVX-512 Byte and Word
AVX512DQ	AVX-512 Doubleword and Quadword Instructions
AVX512VL	AVX-512 Vector Length
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
VMD	Volume Management Device
NM	Node Manager
KPT	Key Protection Technology
PTT	Platform Trust Technology
Run Sure	Run Sure Technology (RAS Capability)
MBE Ctrl	Mode-Based Execute Control
Node Ctrlr	Node Controller Support

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores
Mode	Base	1	2	3	4	5	6	7	8	9	10	11	12
Normal	2,600 MHz	3,700 MHz	3,700 MHz	3,500 MHz	3,500 MHz	3,400 MHz	3,400 MHz	3,400 MHz	3,400 MHz	3,300 MHz	3,300 MHz	3,300 MHz	3,300 MHz
AVX2	2,200 MHz	3,600 MHz	3,600 MHz	3,400 MHz	3,400 MHz	3,300 MHz	3,300 MHz	3,300 MHz	3,300 MHz	2,900 MHz	2,900 MHz	2,900 MHz	2,900 MHz
AVX512	1,700 MHz	3,500 MHz	3,500 MHz	3,300 MHz	3,300 MHz	2,600 MHz	2,600 MHz	2,600 MHz	2,600 MHz	2,300 MHz	2,300 MHz	2,300 MHz	2,300 MHz

@@ Line 1: / Line 1: @@
 {{intel title|Xeon Gold 6126T}}
-{{mpu
+{{chip
-|future=Yes
 |name=Xeon Gold 6126T
-|no image=Yes
+|image=skylake sp (basic).png
 |designer=Intel
 |manufacturer=Intel
@@ Line 9: / Line 8: @@
 |part number=CD8067303593100
 |s-spec=SR3J9
+|s-spec qs=QN39
 |market=Server
 |first announced=April 25, 2017
+|first launched=July 11, 2017
+|release price=$1865.00
 |family=Xeon Gold
 |series=6100
 |locked=Yes
-|frequency=2.6 GHz
+|frequency=2,600 MHz
+|turbo frequency1=3,700 MHz
 |bus type=DMI 3.0
 |bus links=4
 |bus rate=8 GT/s
 |clock multiplier=26
+|cpuid=0x50654
 |isa=x86-64
 |isa family=x86
-|microarch=Skylake
+|microarch=Skylake (server)
 |platform=Purley
 |chipset=Lewisburg
@@ Line 32: / Line 36: @@
 |core count=12
 |thread count=24
-|package module 1={{packages/intel/fclga-3647}}
+|max memory=768 GiB
+|max cpus=4
+|smp interconnect=UPI
+|smp interconnect links=3
+|smp interconnect rate=10.4 GT/s
+|tdp=125 W
+|tcase min=0 °C
+|tcase max=74 °C
+|package name 1=intel,fclga_3647
 }}
-'''Xeon Gold 6126T''' is a {{arch|64}} [[x86]] [[dodeca-core]] high-performance server [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6126T operates at 2.6 GHz
+'''Xeon Gold 6126T''' is a {{arch|64}} [[dodeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6126T, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.6 GHz with a TDP of 125 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
+This specific model (''T'') has 10 years extended life guarantees designed to be [[NEBS]]-friendly for use in [[NEBS]]-complaint applications.
-{{unknown features}}
 == Cache ==
-{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
+{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
+The Xeon Gold 6126T features a considerably larger non-default 19.25 MiB of [[L3]], a size that would normally be found on a 14-core part.
 {{cache size
 |l1 cache=768 KiB
@@ Line 54: / Line 66: @@
 |l2 desc=16-way set associative
 |l2 policy=write-back
-|l3 cache=16.5 MiB
+|l3 cache=19.25 MiB
-|l3 break=10x1.375 MiB
+|l3 break=14x1.375 MiB
 |l3 desc=11-way set associative
 |l3 policy=write-back
 }}
+== Memory controller ==
+{{memory controller
+|type=DDR4-2666
+|ecc=Yes
+|max mem=768 GiB
+|controllers=2
+|channels=6
+|max bandwidth=119.21 GiB/s
+|bandwidth schan=19.87 GiB/s
+|bandwidth dchan=39.74 GiB/s
+|bandwidth qchan=79.47 GiB/s
+|bandwidth hchan=119.21 GiB/s
+}}
+== Expansions ==
+{{expansions
+| pcie revision      = 3.0
+| pcie lanes         = 48
+| pcie config        = x16
+| pcie config 2      = x8
+| pcie config 3      = x4
+}}
 == Features ==
@@ Line 82: / Line 116: @@
 |avx=Yes
 |avx2=Yes
+|avx512f=Yes
+|avx512cd=Yes
+|avx512er=No
+|avx512pf=No
+|avx512bw=Yes
+|avx512dq=Yes
+|avx512vl=Yes
+|avx512ifma=No
+|avx512vbmi=No
+|avx5124fmaps=No
+|avx5124vnniw=No
+|avx512vpopcntdq=No
 |abm=Yes
 |tbm=No
@@ Line 97: / Line 142: @@
 |f16c=Yes
 |tbt1=No
-|tbt2=No
+|tbt2=Yes
 |tbmt3=No
 |bpt=No
 |eist=Yes
-|sst=No
+|sst=Yes
 |flex=No
 |fastmem=No
+|ivmd=Yes
+|intelnodecontroller=Yes
+|intelnode=Yes
+|kpt=Yes
+|ptt=Yes
+|intelrunsure=Yes
+|mbe=Yes
 |isrt=No
 |sba=No
@@ Line 111: / Line 163: @@
 |ipt=No
 |tsx=Yes
-|txt=No
+|txt=Yes
 |ht=Yes
 |vpro=Yes
@@ Line 117: / Line 169: @@
 |vtd=Yes
 |ept=Yes
-|mpx=Yes
+|mpx=No
 |sgx=No
 |securekey=No
-|osguard=Yes
+|osguard=No
 |3dnow=No
 |e3dnow=No
@@ Line 127: / Line 179: @@
 |amdvi=No
 |amdv=No
+|amdsme=No
+|amdtsme=No
+|amdsev=No
 |rvi=No
 |smt=No
@@ Line 132: / Line 187: @@
 |xfr=No
 }}
+== Frequencies ==
+{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
+{{frequency table
+|freq_base=2,600 MHz
+|freq_1=3,700 MHz
+|freq_2=3,700 MHz
+|freq_3=3,500 MHz
+|freq_4=3,500 MHz
+|freq_5=3,400 MHz
+|freq_6=3,400 MHz
+|freq_7=3,400 MHz
+|freq_8=3,400 MHz
+|freq_9=3,300 MHz
+|freq_10=3,300 MHz
+|freq_11=3,300 MHz
+|freq_12=3,300 MHz
+|freq_avx2_base=2,200 MHz
+|freq_avx2_1=3,600 MHz
+|freq_avx2_2=3,600 MHz
+|freq_avx2_3=3,400 MHz
+|freq_avx2_4=3,400 MHz
+|freq_avx2_5=3,300 MHz
+|freq_avx2_6=3,300 MHz
+|freq_avx2_7=3,300 MHz
+|freq_avx2_8=3,300 MHz
+|freq_avx2_9=2,900 MHz
+|freq_avx2_10=2,900 MHz
+|freq_avx2_11=2,900 MHz
+|freq_avx2_12=2,900 MHz
+|freq_avx512_base=1,700 MHz
+|freq_avx512_1=3,500 MHz
+|freq_avx512_2=3,500 MHz
+|freq_avx512_3=3,300 MHz
+|freq_avx512_4=3,300 MHz
+|freq_avx512_5=2,600 MHz
+|freq_avx512_6=2,600 MHz
+|freq_avx512_7=2,600 MHz
+|freq_avx512_8=2,600 MHz
+|freq_avx512_9=2,300 MHz
+|freq_avx512_10=2,300 MHz
+|freq_avx512_11=2,300 MHz
+|freq_avx512_12=2,300 MHz
+}}
+[[Category:microprocessor models by intel based on skylake extreme core count die]]

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 6126T - Intel#io +
base frequency	2,600 MHz (2.6 GHz, 2,600,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	26 +
core count	12 +
core family	6 +
core name	Skylake SP +
core stepping	H0 +
cpuid	0x50654 +
designer	Intel +
family	Xeon Gold +
first announced	April 25, 2017 +
first launched	July 11, 2017 +
full page name	intel/xeon gold/6126t +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	768 KiB (786,432 B, 0.75 MiB) +
l1d$ description	8-way set associative +
l1d$ size	384 KiB (393,216 B, 0.375 MiB) +
l1i$ description	8-way set associative +
l1i$ size	384 KiB (393,216 B, 0.375 MiB) +
l2$ description	16-way set associative +
l2$ size	12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description	11-way set associative +
l3$ size	19.25 MiB (19,712 KiB, 20,185,088 B, 0.0188 GiB) +
ldate	July 11, 2017 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	347.15 K (74 °C, 165.2 °F, 624.87 °R) +
max cpu count	4 +
max memory	786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
max pcie lanes	48 +
microarchitecture	Skylake (server) +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	6126T +
name	Xeon Gold 6126T +
package	FCLGA-3647 +
part number	CD8067303593100 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 1,865.00 (€ 1,678.50, £ 1,510.65, ¥ 192,710.45) +
s-spec	SR3J9 +
s-spec (qs)	QN39 +
series	6100 +
smp interconnect	UPI +
smp interconnect links	3 +
smp interconnect rate	10.4 GT/s +
smp max ways	4 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2666 +
tdp	125 W (125,000 mW, 0.168 hp, 0.125 kW) +
technology	CMOS +
thread count	24 +
turbo frequency (1 core)	3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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