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Difference between revisions of "intel/xeon gold/6140m"
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{{intel title|Xeon Gold 6140M}}
 
{{intel title|Xeon Gold 6140M}}
−
{{mpu
+
{{chip
−
|future=Yes
 
 
|name=Xeon Gold 6140M
 
|name=Xeon Gold 6140M
−
|no image=Yes
+
|image=skylake sp (basic).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
Line 9: Line 8:
 
|part number=CD8067303405500
 
|part number=CD8067303405500
 
|s-spec=SR3AZ
 
|s-spec=SR3AZ
 +
|s-spec qs=QMRU
 
|market=Server
 
|market=Server
 
|first announced=April 25, 2017
 
|first announced=April 25, 2017
 +
|first launched=July 11, 2017
 +
|release price=$5448.00
 
|family=Xeon Gold
 
|family=Xeon Gold
 
|series=6100
 
|series=6100
 
|locked=Yes
 
|locked=Yes
−
|frequency=2.3 GHz
+
|frequency=2,300 MHz
−
|bus type=DMI 3.0
+
|turbo frequency1=3,700 MHz
−
|bus links=4
 
−
|bus rate=8 GT/s
 
 
|clock multiplier=23
 
|clock multiplier=23
 +
|cpuid=0x50654
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
−
|microarch=Skylake
+
|microarch=Skylake (server)
 
|platform=Purley
 
|platform=Purley
 
|chipset=Lewisburg
 
|chipset=Lewisburg
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|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
−
|die area=<!-- XX mm² -->
 
 
|word size=64 bit
 
|word size=64 bit
 +
|core count=18
 +
|thread count=36
 +
|max memory=1,536 GiB
 
|max cpus=4
 
|max cpus=4
−
|v core tolerance=<!-- OR ... -->
+
|smp interconnect=UPI
−
|v io 2=<!-- OR ... -->
+
|smp interconnect links=3
−
|temp min=<!-- use TJ/TC whenever possible instead -->
+
|smp interconnect rate=10.4 GT/s
−
|tjunc min=<!-- .. °C -->
+
|tdp=140 W
−
|package module 2=<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
+
|tcase min=0 °C
−
|package module 1={{packages/intel/fclga-3647}}
+
|tcase max=91 °C
 +
|dts min=0 °C
 +
|dts max=101 °C
 +
|package name 1=intel,fclga_3647
 +
|successor=Xeon Gold 6240M
 +
|successor link=intel/xeon_gold/6240m
 
}}
 
}}
−
'''Xeon Gold 6140M''' is a {{arch|64}} [[x86]] high-performance server [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6140M operates at 2.3 GHz
+
'''Xeon Gold 6140M''' is a {{arch|64}} [[18-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6140M, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.3 GHz with a TDP of 140 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 1.5 TiB of hexa-channel DDR4-2666 ECC memory.
  
 +
As indicated by the ''M'' suffix, this specific model supports double the memory capacity for up to 1.5 TiB per socket.
 +
== Cache ==
 +
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
 +
{{cache size
 +
|l1 cache=1.125 MiB
 +
|l1i cache=576 KiB
 +
|l1i break=18x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=576 KiB
 +
|l1d break=18x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=18 MiB
 +
|l2 break=18x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=24.75 MiB
 +
|l3 break=18x1.375 MiB
 +
|l3 desc=11-way set associative
 +
|l3 policy=write-back
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2666
 +
|ecc=Yes
 +
|max mem=1,536 GiB
 +
|controllers=2
 +
|channels=6
 +
|max bandwidth=119.21 GiB/s
 +
|bandwidth schan=19.87 GiB/s
 +
|bandwidth dchan=39.74 GiB/s
 +
|bandwidth qchan=79.47 GiB/s
 +
|bandwidth hchan=119.21 GiB/s
 +
}}
  
−
{{unknown features}}
+
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 48
 +
| pcie config        = x16
 +
| pcie config 2      = x8
 +
| pcie config 3      = x4
 +
}}
  
 
== Features ==  
 
== Features ==  
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|avx=Yes
 
|avx=Yes
 
|avx2=Yes
 
|avx2=Yes
−
|avx512=Yes
+
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 
|abm=Yes
 
|abm=Yes
 
|tbm=No
 
|tbm=No
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|f16c=Yes
 
|f16c=Yes
 
|tbt1=No
 
|tbt1=No
−
|tbt2=No
+
|tbt2=Yes
 
|tbmt3=No
 
|tbmt3=No
 
|bpt=No
 
|bpt=No
 
|eist=Yes
 
|eist=Yes
−
|sst=No
+
|sst=Yes
 
|flex=No
 
|flex=No
 
|fastmem=No
 
|fastmem=No
 +
|ivmd=Yes
 +
|intelnodecontroller=Yes
 +
|intelnode=Yes
 +
|kpt=Yes
 +
|ptt=Yes
 +
|intelrunsure=Yes
 +
|mbe=Yes
 
|isrt=No
 
|isrt=No
 
|sba=No
 
|sba=No
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|ipt=No
 
|ipt=No
 
|tsx=Yes
 
|tsx=Yes
−
|txt=No
+
|txt=Yes
 
|ht=Yes
 
|ht=Yes
 
|vpro=Yes
 
|vpro=Yes
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|vtd=Yes
 
|vtd=Yes
 
|ept=Yes
 
|ept=Yes
−
|mpx=Yes
+
|mpx=No
 
|sgx=No
 
|sgx=No
 
|securekey=No
 
|securekey=No
−
|osguard=Yes
+
|osguard=No
 
|3dnow=No
 
|3dnow=No
 
|e3dnow=No
 
|e3dnow=No
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|amdvi=No
 
|amdvi=No
 
|amdv=No
 
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 
|rvi=No
 
|rvi=No
 
|smt=No
 
|smt=No
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|xfr=No
 
|xfr=No
 
}}
 
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=2,300 MHz
 +
|freq_1=3,700 MHz
 +
|freq_2=3,700 MHz
 +
|freq_3=3,500 MHz
 +
|freq_4=3,500 MHz
 +
|freq_5=3,400 MHz
 +
|freq_6=3,400 MHz
 +
|freq_7=3,400 MHz
 +
|freq_8=3,400 MHz
 +
|freq_9=3,400 MHz
 +
|freq_10=3,400 MHz
 +
|freq_11=3,400 MHz
 +
|freq_12=3,400 MHz
 +
|freq_13=3,100 MHz
 +
|freq_14=3,100 MHz
 +
|freq_15=3,100 MHz
 +
|freq_16=3,100 MHz
 +
|freq_17=3,000 MHz
 +
|freq_18=3,000 MHz
 +
|freq_avx2_base=1,900 MHz
 +
|freq_avx2_1=3,600 MHz
 +
|freq_avx2_2=3,600 MHz
 +
|freq_avx2_3=3,400 MHz
 +
|freq_avx2_4=3,400 MHz
 +
|freq_avx2_5=3,300 MHz
 +
|freq_avx2_6=3,300 MHz
 +
|freq_avx2_7=3,300 MHz
 +
|freq_avx2_8=3,300 MHz
 +
|freq_avx2_9=3,000 MHz
 +
|freq_avx2_10=3,000 MHz
 +
|freq_avx2_11=3,000 MHz
 +
|freq_avx2_12=3,000 MHz
 +
|freq_avx2_13=2,700 MHz
 +
|freq_avx2_14=2,700 MHz
 +
|freq_avx2_15=2,700 MHz
 +
|freq_avx2_16=2,700 MHz
 +
|freq_avx2_17=2,600 MHz
 +
|freq_avx2_18=2,600 MHz
 +
|freq_avx512_base=1,500 MHz
 +
|freq_avx512_1=3,500 MHz
 +
|freq_avx512_2=3,500 MHz
 +
|freq_avx512_3=3,300 MHz
 +
|freq_avx512_4=3,300 MHz
 +
|freq_avx512_5=2,800 MHz
 +
|freq_avx512_6=2,800 MHz
 +
|freq_avx512_7=2,800 MHz
 +
|freq_avx512_8=2,800 MHz
 +
|freq_avx512_9=2,400 MHz
 +
|freq_avx512_10=2,400 MHz
 +
|freq_avx512_11=2,400 MHz
 +
|freq_avx512_12=2,400 MHz
 +
|freq_avx512_13=2,100 MHz
 +
|freq_avx512_14=2,100 MHz
 +
|freq_avx512_15=2,100 MHz
 +
|freq_avx512_16=2,100 MHz
 +
|freq_avx512_17=2,100 MHz
 +
|freq_avx512_18=2,100 MHz
 +
}}
 +
 +
[[Category:microprocessor models by intel based on skylake extreme core count die]]

Latest revision as of 00:45, 29 December 2019

Edit Values
Xeon Gold 6140M
skylake sp (basic).png
General Info
DesignerIntel
ManufacturerIntel
Model Number6140M
Part NumberCD8067303405500
S-SpecSR3AZ
QMRU (QS)
MarketServer
IntroductionApril 25, 2017 (announced)
July 11, 2017 (launched)
Release Price$5448.00
ShopAmazon
General Specs
FamilyXeon Gold
Series6100
LockedYes
Frequency2,300 MHz
Turbo Frequency3,700 MHz (1 core)
Clock multiplier23
CPUID0x50654
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
PlatformPurley
ChipsetLewisburg
Core NameSkylake SP
Core Family6
Core SteppingH0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores18
Threads36
Max Memory1,536 GiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
InterconnectUPI
Interconnect Links3
Interconnect Rate10.4 GT/s
Electrical
TDP140 W
Tcase0 °C – 91 °C
TDTS0 °C – 101 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Gold 6140M is a 64-bit 18-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6140M, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.3 GHz with a TDP of 140 W and a turbo boost frequency of up to 3.7 GHz, supports up 1.5 TiB of hexa-channel DDR4-2666 ECC memory.

As indicated by the M suffix, this specific model supports double the memory capacity for up to 1.5 TiB per socket.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.125 MiB
1,152 KiB
1,179,648 B
L1I$576 KiB
589,824 B
0.563 MiB
18x32 KiB8-way set associative 
L1D$576 KiB
589,824 B
0.563 MiB
18x32 KiB8-way set associativewrite-back
L2$18 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
  18x1 MiB16-way set associativewrite-back
L3$24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
  18x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem1,536 GiB
Controllers2
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
Node CtrlrNode Controller Support

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
123456789101112131415161718
Normal2,300 MHz3,700 MHz3,700 MHz3,500 MHz3,500 MHz3,400 MHz3,400 MHz3,400 MHz3,400 MHz3,400 MHz3,400 MHz3,400 MHz3,400 MHz3,100 MHz3,100 MHz3,100 MHz3,100 MHz3,000 MHz3,000 MHz
AVX21,900 MHz3,600 MHz3,600 MHz3,400 MHz3,400 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz3,000 MHz3,000 MHz3,000 MHz3,000 MHz2,700 MHz2,700 MHz2,700 MHz2,700 MHz2,600 MHz2,600 MHz
AVX5121,500 MHz3,500 MHz3,500 MHz3,300 MHz3,300 MHz2,800 MHz2,800 MHz2,800 MHz2,800 MHz2,400 MHz2,400 MHz2,400 MHz2,400 MHz2,100 MHz2,100 MHz2,100 MHz2,100 MHz2,100 MHz2,100 MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/6140m&oldid=95140"
Facts about "Xeon Gold 6140M - Intel"
RDF feed
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions + and OS Guard +
has intel enhanced speedstep technologytrue +
has intel supervisor mode execution protectiontrue +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
x86/has memory protection extensionstrue +