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Difference between revisions of "intel/xeon gold/6130t"
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{{intel title|Xeon Gold 6130T}}
 
{{intel title|Xeon Gold 6130T}}
−
{{mpu
+
{{chip
−
|future=Yes
 
 
|name=Xeon Gold 6130T
 
|name=Xeon Gold 6130T
−
|no image=Yes
+
|image=skylake sp (basic).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
Line 9: Line 8:
 
|part number=CD8067303593000
 
|part number=CD8067303593000
 
|s-spec=SR3J8
 
|s-spec=SR3J8
 +
|s-spec qs=QN38
 
|market=Server
 
|market=Server
−
|first announced=April 25, 2017
+
|first announced=July 11, 2017
 +
|first launched=July 11, 2017
 +
|release price=$1988.00
 
|family=Xeon Gold
 
|family=Xeon Gold
 
|series=6100
 
|series=6100
 
|locked=Yes
 
|locked=Yes
−
|frequency=2.1 GHz
+
|frequency=2,100 MHz
−
|bus type=DMI 3.0
+
|turbo frequency1=3,700 MHz
−
|bus links=4
 
−
|bus rate=8 GT/s
 
 
|clock multiplier=21
 
|clock multiplier=21
 +
|cpuid=0x50654
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
−
|microarch=Skylake
+
|microarch=Skylake (server)
 
|platform=Purley
 
|platform=Purley
 
|chipset=Lewisburg
 
|chipset=Lewisburg
Line 29: Line 30:
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
−
|die area=<!-- XX mm² -->
 
 
|word size=64 bit
 
|word size=64 bit
 +
|core count=16
 +
|thread count=32
 +
|max memory=768 GiB
 
|max cpus=4
 
|max cpus=4
−
|v core tolerance=<!-- OR ... -->
+
|smp interconnect=UPI
−
|v io 2=<!-- OR ... -->
+
|smp interconnect links=3
−
|temp min=<!-- use TJ/TC whenever possible instead -->
+
|smp interconnect rate=10.4 GT/s
−
|tjunc min=<!-- .. °C -->
+
|tdp=125 W
−
|package module 2=<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
+
|tcase min=0 °C
−
|packaging=Yes
+
|tcase max=77 °C
−
|package 0=FCLGA-3647
+
|package name 1=intel,fclga_3647
−
|package 0 type=LGA
+
|successor=Xeon Gold 6230T
−
|package 0 pins=3647
+
|successor link=intel/xeon_gold/6230t
−
|socket 0=LGA-3647
 
−
|socket 0 type=LGA
 
 
}}
 
}}
−
'''Xeon Gold 6130T''' is a {{arch|64}} [[x86]] high-performance server [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6130T operates at 2.1 GHz
+
'''Xeon Gold 6130T''' is a {{arch|64}} [[16-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6130T, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 125 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
  
 +
This specific model (''T'') has 10 years extended life guarantees designed to be [[NEBS]]-friendly for use in [[NEBS]]-complaint applications.
  
−
{{unknown features}}
+
== Cache ==
 +
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
 +
{{cache size
 +
|l1 cache=1 MiB
 +
|l1i cache=512 KiB
 +
|l1i break=16x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=512 KiB
 +
|l1d break=16x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=16 MiB
 +
|l2 break=16x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=22 MiB
 +
|l3 break=16x1.375 MiB
 +
|l3 desc=11-way set associative
 +
|l3 policy=write-back
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2666
 +
|ecc=Yes
 +
|max mem=768 GiB
 +
|controllers=2
 +
|channels=6
 +
|max bandwidth=119.21 GiB/s
 +
|bandwidth schan=19.87 GiB/s
 +
|bandwidth dchan=39.74 GiB/s
 +
|bandwidth qchan=79.47 GiB/s
 +
|bandwidth hchan=119.21 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 48
 +
| pcie config        = x16
 +
| pcie config 2      = x8
 +
| pcie config 3      = x4
 +
}}
  
 
== Features ==  
 
== Features ==  
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|avx=Yes
 
|avx=Yes
 
|avx2=Yes
 
|avx2=Yes
−
|avx512=Yes
+
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 
|abm=Yes
 
|abm=Yes
 
|tbm=No
 
|tbm=No
Line 85: Line 140:
 
|f16c=Yes
 
|f16c=Yes
 
|tbt1=No
 
|tbt1=No
−
|tbt2=No
+
|tbt2=Yes
 
|tbmt3=No
 
|tbmt3=No
 
|bpt=No
 
|bpt=No
 
|eist=Yes
 
|eist=Yes
−
|sst=No
+
|sst=Yes
 
|flex=No
 
|flex=No
 
|fastmem=No
 
|fastmem=No
 +
|ivmd=Yes
 +
|intelnodecontroller=Yes
 +
|intelnode=Yes
 +
|kpt=Yes
 +
|ptt=Yes
 +
|intelrunsure=Yes
 +
|mbe=Yes
 
|isrt=No
 
|isrt=No
 
|sba=No
 
|sba=No
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|ipt=No
 
|ipt=No
 
|tsx=Yes
 
|tsx=Yes
−
|txt=No
+
|txt=Yes
 
|ht=Yes
 
|ht=Yes
 
|vpro=Yes
 
|vpro=Yes
Line 105: Line 167:
 
|vtd=Yes
 
|vtd=Yes
 
|ept=Yes
 
|ept=Yes
−
|mpx=Yes
+
|mpx=No
 
|sgx=No
 
|sgx=No
 
|securekey=No
 
|securekey=No
−
|osguard=Yes
+
|osguard=No
 
|3dnow=No
 
|3dnow=No
 
|e3dnow=No
 
|e3dnow=No
Line 115: Line 177:
 
|amdvi=No
 
|amdvi=No
 
|amdv=No
 
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 
|rvi=No
 
|rvi=No
 
|smt=No
 
|smt=No
Line 120: Line 185:
 
|xfr=No
 
|xfr=No
 
}}
 
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=2,100 MHz
 +
|freq_1=3,700 MHz
 +
|freq_2=3,700 MHz
 +
|freq_3=3,500 MHz
 +
|freq_4=3,500 MHz
 +
|freq_5=3,400 MHz
 +
|freq_6=3,400 MHz
 +
|freq_7=3,400 MHz
 +
|freq_8=3,400 MHz
 +
|freq_9=3,100 MHz
 +
|freq_10=3,100 MHz
 +
|freq_11=3,100 MHz
 +
|freq_12=3,100 MHz
 +
|freq_13=2,800 MHz
 +
|freq_14=2,800 MHz
 +
|freq_15=2,800 MHz
 +
|freq_16=2,800 MHz
 +
|freq_avx2_base=1,700 MHz
 +
|freq_avx2_1=3,600 MHz
 +
|freq_avx2_2=3,600 MHz
 +
|freq_avx2_3=3,400 MHz
 +
|freq_avx2_4=3,400 MHz
 +
|freq_avx2_5=3,100 MHz
 +
|freq_avx2_6=3,100 MHz
 +
|freq_avx2_7=3,100 MHz
 +
|freq_avx2_8=3,100 MHz
 +
|freq_avx2_9=2,600 MHz
 +
|freq_avx2_10=2,600 MHz
 +
|freq_avx2_11=2,600 MHz
 +
|freq_avx2_12=2,600 MHz
 +
|freq_avx2_13=2,400 MHz
 +
|freq_avx2_14=2,400 MHz
 +
|freq_avx2_15=2,400 MHz
 +
|freq_avx2_16=2,400 MHz
 +
|freq_avx512_base=1,300 MHz
 +
|freq_avx512_1=3,500 MHz
 +
|freq_avx512_2=3,500 MHz
 +
|freq_avx512_3=3,100 MHz
 +
|freq_avx512_4=3,100 MHz
 +
|freq_avx512_5=2,400 MHz
 +
|freq_avx512_6=2,400 MHz
 +
|freq_avx512_7=2,400 MHz
 +
|freq_avx512_8=2,400 MHz
 +
|freq_avx512_9=2,100 MHz
 +
|freq_avx512_10=2,100 MHz
 +
|freq_avx512_11=2,100 MHz
 +
|freq_avx512_12=2,100 MHz
 +
|freq_avx512_13=1,900 MHz
 +
|freq_avx512_14=1,900 MHz
 +
|freq_avx512_15=1,900 MHz
 +
|freq_avx512_16=1,900 MHz
 +
}}
 +
 +
[[Category:microprocessor models by intel based on skylake extreme core count die]]

Latest revision as of 00:20, 29 December 2019

Edit Values
Xeon Gold 6130T
skylake sp (basic).png
General Info
DesignerIntel
ManufacturerIntel
Model Number6130T
Part NumberCD8067303593000
S-SpecSR3J8
QN38 (QS)
MarketServer
IntroductionJuly 11, 2017 (announced)
July 11, 2017 (launched)
Release Price$1988.00
ShopAmazon
General Specs
FamilyXeon Gold
Series6100
LockedYes
Frequency2,100 MHz
Turbo Frequency3,700 MHz (1 core)
Clock multiplier21
CPUID0x50654
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
PlatformPurley
ChipsetLewisburg
Core NameSkylake SP
Core Family6
Core SteppingH0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores16
Threads32
Max Memory768 GiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
InterconnectUPI
Interconnect Links3
Interconnect Rate10.4 GT/s
Electrical
TDP125 W
Tcase0 °C – 77 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Gold 6130T is a 64-bit 16-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6130T, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.1 GHz with a TDP of 125 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

This specific model (T) has 10 years extended life guarantees designed to be NEBS-friendly for use in NEBS-complaint applications.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1 MiB
1,024 KiB
1,048,576 B
L1I$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associative 
L1D$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associativewrite-back
L2$16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
  16x1 MiB16-way set associativewrite-back
L3$22 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
  16x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem768 GiB
Controllers2
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
Node CtrlrNode Controller Support

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
12345678910111213141516
Normal2,100 MHz3,700 MHz3,700 MHz3,500 MHz3,500 MHz3,400 MHz3,400 MHz3,400 MHz3,400 MHz3,100 MHz3,100 MHz3,100 MHz3,100 MHz2,800 MHz2,800 MHz2,800 MHz2,800 MHz
AVX21,700 MHz3,600 MHz3,600 MHz3,400 MHz3,400 MHz3,100 MHz3,100 MHz3,100 MHz3,100 MHz2,600 MHz2,600 MHz2,600 MHz2,600 MHz2,400 MHz2,400 MHz2,400 MHz2,400 MHz
AVX5121,300 MHz3,500 MHz3,500 MHz3,100 MHz3,100 MHz2,400 MHz2,400 MHz2,400 MHz2,400 MHz2,100 MHz2,100 MHz2,100 MHz2,100 MHz1,900 MHz1,900 MHz1,900 MHz1,900 MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/6130t&oldid=95133"
Facts about "Xeon Gold 6130T - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 6130T - Intel#io +
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
chipsetLewisburg +
clock multiplier21 +
core count16 +
core family6 +
core nameSkylake SP +
core steppingH0 +
cpuid0x50654 +
designerIntel +
familyXeon Gold +
first announcedJuly 11, 2017 +
first launchedJuly 11, 2017 +
full page nameintel/xeon gold/6130t +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size1,024 KiB (1,048,576 B, 1 MiB) +
l1d$ description8-way set associative +
l1d$ size512 KiB (524,288 B, 0.5 MiB) +
l1i$ description8-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description16-way set associative +
l2$ size16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
l3$ description11-way set associative +
l3$ size22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) +
ldateJuly 11, 2017 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer +
max case temperature350.15 K (77 °C, 170.6 °F, 630.27 °R) +
max cpu count4 +
max memory786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureSkylake (server) +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number6130T +
nameXeon Gold 6130T +
packageFCLGA-3647 +
part numberCD8067303593000 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 1,988.00 (€ 1,789.20, £ 1,610.28, ¥ 205,420.04) +
s-specSR3J8 +
s-spec (qs)QN38 +
series6100 +
smp interconnectUPI +
smp interconnect links3 +
smp interconnect rate10.4 GT/s +
smp max ways4 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2666 +
tdp125 W (125,000 mW, 0.168 hp, 0.125 kW) +
technologyCMOS +
thread count32 +
turbo frequency (1 core)3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +