Difference between revisions of "arm/armv1"

Latest revision as of 14:07, 2 July 2017

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ARMv1 is the first ARM instruction set version. Introduced with the ARM1 on April 26 1985, the ARMv1 defines a 32-bit ISA along with 26-bit addressing space. The ARMv1 was only implemented by the ARM1 and was replaced soon after by the ARM2. Only a few hundred of those chips were ever fabricated.

Overview[edit]

The ARMv1 presents a simple instruction set architecture, albeit bigger and more complex than many of its RISC contemporaries, consisting of mostly simple operations along with a number of complex ones borrowed from early 8-bit CISC microprocessors. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a 24-bit program counter allowing for a 26-bit address space of up to 64 MiB of memory.

Registers[edit]

There are 16 general purpose 32-bit registers. With the exception of register 15 and 14, all registers are orthogonal with no specific designated purpose.

Addressing Mode[edit]

The ARMv1 has five addressing modes:

Mode	Syntax	Operation
PC Relative	Label	Effective_Address = PC ± Offset (12 bits)
Base Register Offset With Post-Increment	[Rn], offset	Effective_Address = Rn Rn = Rn ± offset
Base Register Offset With Pre-Increment	[Rn, offset]	Effective_Address = Rn ± offset (12 bits) Rn = Rn ± offset
Base Register Index With Post-Increment	[Rn], Rm	Effective_Address = Rn Rn = Rn ± Rm
Base Register Index With Pre-Increment	[Rn, Rm]	Effective_Address = Rn ± Rm Rn = Rn ± Rm

Instruction Listing[edit]

The ARMv1 ISA has 45 operations under 23 mnemonics. The ARMv1 is broken down into 8 classes of instruction:

Movement Instructions
Load Instructions
Store Instructions
Arithmetic Instructions
Logical Instructions
Comparison Instructions
Branch Instructions
Miscellaneous Instructions

ARMv1 ISA
Mnemonic	Syntax	Description	Action
Movement Instructions Movement instructions move data between registers and operands.
MOV	MOV<cond>{S} Rd, #imm	Move value immed	Rd = immed
MOV	MOV<cond>{S} Rd, Rm, {, <shift>}	Move value	Rd = Shift(Rm)
MVN	MVN<cond>{S} Rd, #imm	Move NOT value immed	Rd = ¬immed
MVN	MVN<cond>{S} Rd, Rm, {, <shift>}	Move NOT value	Rd = ¬Shift(Rm)
Load Instructions Load instructions move the content of memory addresses into registers.
LDM	LDM<cond><type> Rn{!}, <reglist>{^}	Load multiple	addr = Rn for each Rd in {reglist}: Rd = [addr] update address based on {type}
LDR	LDR<cond>{B} Rd, [Rn {, #imm}]{!}	Load register immed	Rd = [Rn + imm] If !: Rn = Rn + imm
LDR	LDR<cond>{B} Rd, [Rn, Rm {, <shift>}]{!}	Load register	Rd = [Rn + Shift(Rm)] If !: Rn = Rn + Shift(Rm)]
LDR	LDR<cond>{B}{T} Rd, [Rn], #imm	Load register, post index	Rd = [Rn] Rn = Rn + imm
LDR	LDR<cond>{B}{T} Rd, [Rn], Rm {, <shift>}	Load register, post index	Rd = [Rn] Rn = Rn + Shift(Rm)
Store Instructions Store instructions moves the values from registers into memory.
STM	STM<cond><type> Rn{!}, <reglist>{^}	Store multiple	addr = Rn for each Rd in {reglist}: [addr] = Rd update address based on {type}
STR	STR<cond>{B} Rd, [Rn {, #imm}]{!}	Store register immed	[Rn + imm] = Rd If !: Rn = Rn + imm
STR	STR<cond>{B} Rd, [Rn, Rm {, <shift>}]{!}	Store register	[Rn + Shift(Rm)] = Rd If !: Rn = Rn + Shift(Rm)]
STR	STR<cond>{B}{T} Rd, [Rn], #imm	Store register, post index	[Rn] = Rd Rn = Rn + imm
STR	STR<cond>{B}{T} Rd, [Rn], Rm {, <shift>}	Store register, post index	[Rn] = Rd Rn = Rn + Shift(Rm)
Arithmetic Instructions Arithmetic instructions perform basic mathematical operations on two operands.
ADC	ADC<cond>{S} Rd, Rn, #imm	Add and carry immed	Rd = Rn + imm + C
ADC	ADC<cond>{S} Rd, Rn, Rm{, <shift>}	Add and carry	Rd = Rn + Shift(Rm) + C
ADD	ADD<cond>S Rd, Rn, #imm	Add immed	Rd = Rn + imm
ADD	ADD<cond>S Rd, Rn, Rm{, <shift>}	Add	Rd = Rn + Shift(Rm)
RSB	RSB<cond>S Rd, Rn, #imm	Reverse subtract immed	Rd = imm - Rn
RSB	RSB<cond>S Rd, Rn, Rm{, <shift>}	Reverse subtract	Rd = Shift(Rm) - Rn
RSC	RSB<cond>S Rd, Rn, #imm	Reverse subtract with carry immed	Rd = imm - Rn - ¬C
RSC	RSB<cond>S Rd, Rn, Rm{, <shift>}	Reverse subtract with carry	Rd = Shift(Rm) - Rn - ¬C
SBC	SBC<cond>{S} Rd, Rn, #imm	Subtract with carry immed	Rd = Rn - imm - ¬C
SBC	SBC<cond>{S} Rd, Rn, Rm{, <shift>}	Subtract with carry	Rd = Rn - Shift(Rm) - ¬C
SUB	SUB<cond>{S} Rd, Rn, #imm	Subtract immed	Rd = Rn - imm
SUB	SUB<cond>{S} Rd, Rn, Rm{, <shift>}	Subtract	Rd = Rn - Shift(Rm)
Logical Instructions Logical instructions perform logical bitwise operations on operands.
AND	AND<cond>{S} Rd, Rn, #imm	AND immed	Rd = Rn & imm
AND	AND<cond>{S} Rd, Rn, Rm{, <shift>}	AND	Rd = Rn & Shift(Rm)
BIC	BIC<cond>{S} Rd, Rn, #imm	Bit clear immed	Rd = Rn & ¬imm
BIC	BIC<cond>{S} Rd, Rn, Rm{, <shift>}	Bit clear	Rd = Rn & ¬Rm
EOR	EOR<cond>{S} Rd, Rn, #imm	Exclusive OR immed	Rd = Rn ⊕ imm
EOR	EOR<cond>{S} Rd, Rn, Rm{, <shift>}	Exclusive OR	Rd = Rn ⊕ Shift(Rm)
ORR	ORR<cond>{S} Rd, Rn, #imm	Logical OR immed	Rd = Rn ∥ imm
ORR	ORR<cond>{S} Rd, Rn, Rm{, <shift>}	Logical OR	Rd = Rn ∥ Shift(Rm)
Comparison Instructions Comparison instructions compare two values and set appropriate status flags.
CMN	CMN<cond> Rn, #imm	Compare negative immed	CPSR flags set on (Rn + imm)
CMN	CMN<cond> Rn, Rm{, <shift>}	Compare negative	CPSR flags set on (Rn + Shift(Rm))
CMP	CMP<cond> Rn, #imm	Compare immed	CPSR flags set on (Rn - imm)
CMP	CMP<cond> Rn, Rm{, <shift>}	Compare	CPSR flags set on (Rn - Shift(Rm))
TEQ	TEQ<cond> Rn, #imm	Test equality immed	CPSR flags set on (Rn ⊕ imm)
TEQ	TEQ<cond> Rn, Rm{, <shift>}	Test equality	CPSR flags set on (Rn ⊕ Shift(Rm))
TST	TST<cond> Rn, #imm	Test bits immed	CPSR flags set on (Rn & imm)
TST	TST<cond> Rn, Rm{, <shift>}	Test bits	CPSR flags set on (Rn & Shift(Rm))
Branch Instructions Branch instructions order instruction processing to start elsewhere conditionally or unconditionally.
B	B<cond> imm	Branch relative	PC = PC + address
BL	BL<cond> imm	Branch and link relative	LR = RET PC = PC + address
Miscellaneous Instructions Any instruction that doesn't belong anywhere else.
SWI	SWI<cond> imm	Software interrupt	LR = RET Execute SWI vector in supervisor mode

Multiplication and Floating Point[edit]

ARMv1 does not have support for multiplication. Software that requires multiplication will have to resort to a software implementation (e.g., Shift-and-Add Multiplication). This was considerably slow and was consequently added in later ARM versions. Likewise there was no support for hardware floating point or an ability to do such operations on an external FPU coprocessor.

Exception Vector Map[edit]

Address	Function	Priority
000 0000	Reset	0
000 0004	Undefined Instruction Trap	6
000 0008	Software Interrupt	7
000 000C	Abort (Prefetch)	5
000 0010	Abort (Data)	2
000 0014	Address Exception	1
000 0018	Normal Interrupt (IRQ)	4
000 001C	Fast Interrupt (FIRQ)	3

@@ Line 1: / Line 1: @@
-{{arm title|ARMv1}}
+{{arm title|ARMv1}}{{arm isa main}}
-'''ARMv1''' is the first [[ARM]] instruction set version. Introduced with the {{armh|ARM1}} on April 26 1985, the ARMv1 defines a {{arch|32}} ISA along with {{arm|26-bit|26-bit addressing space}}. The ARMv1 was only implemented by the {{armh|ARM1}} and was replaced soon after by the {{armh|ARM2}}. Only a few hundred of those chips were ever fabricated.
+'''ARMv1''' is the first [[ARM]] instruction set version. Introduced with the {{acorn|ARM1}} on April 26 1985, the ARMv1 defines a {{arch|32}} ISA along with {{arm|26-bit|26-bit addressing space}}. The ARMv1 was only implemented by the {{acorn|ARM1}} and was replaced soon after by the {{acorn|ARM2}}. Only a few hundred of those chips were ever fabricated.
 == Overview ==
-The ARMv1 is a simple architecture. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a [[program counter]] which is 26 bits in size allowing for an address space of up to 64 MiB of data.
+The ARMv1 presents a simple instruction set architecture, albeit bigger and more complex than many of its [[RISC]] contemporaries, consisting of mostly simple operations along with a number of complex ones borrowed from early {{arch|8}} CISC microprocessors. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a 24-bit [[program counter]] allowing for a 26-bit address space of up to 64 MiB of memory.
 == Registers ==
-There are 16 [[general purpose registers|general purpose]] 32-bit registers. With the exception of {{arm|R15|register 15}}, all registers are orthogonal with no specific designated purpose.
+There are 16 [[general purpose registers|general purpose]] 32-bit registers. With the exception of {{arm|R15|register 15}} and 14, all registers are orthogonal with no specific designated purpose.
+== Addressing Mode ==
+The ARMv1 has five addressing modes:
+{| class="wikitable"
+|-
+! Mode !! Syntax !! Operation
+|-
+| PC Relative || Label || Effective_Address = PC ± Offset (12 bits)
+|-
+| Base Register Offset<br>With Post-Increment || [Rn], offset || Effective_Address = Rn<br>Rn = Rn ± offset
+|-
+| Base Register Offset<br>With Pre-Increment || [Rn, offset] || Effective_Address = Rn ± offset (12 bits)<br>Rn = Rn ± offset
+|-
+| Base Register Index<br>With Post-Increment || [Rn], Rm || Effective_Address = Rn<br>Rn = Rn ± Rm
+|-
+| Base Register Index<br>With Pre-Increment || [Rn, Rm] || Effective_Address = Rn ± Rm<br>Rn = Rn ± Rm
+|}
 == Instruction Listing ==
-The ARMv1 is broken down into 8 classes of instruction:
+The ARMv1 ISA has 45 operations under 23 mnemonics. The ARMv1 is broken down into 8 classes of instruction:
 * [[#movement_instructions|Movement Instructions]]
@@ Line 28: / Line 46: @@
 | listing  =
-{{inst|cols=5|section=<span id="movement_instructions">'''Movement Instructions'''</span>}}
+{{inst|cols=5|section=<span id="movement_instructions">'''Movement Instructions'''</span><br><small>Movement instructions move data between registers and operands.</small>}}
 {{inst|mn=MOV |col 1=MOV<cond>{S} Rd, #imm            |col 2=Move value immed     |col 3 = Rd = immed}}
-{{inst|mn=MOV |col 1=MOV<cond>{S} Rd, Rm, {, <shift>} |col 2=Move value           |col 3 = Rd = {shifted Rm} }}
+{{inst|mn=MOV |col 1=MOV<cond>{S} Rd, Rm, {, <shift>} |col 2=Move value           |col 3 = Rd = Shift(Rm) }}
 {{inst|mn=MVN |col 1=MVN<cond>{S} Rd, #imm            |col 2=Move NOT value immed |col 3 = Rd = {{l|not|immed}}}}
-{{inst|mn=MVN |col 1=MVN<cond>{S} Rd, Rm, {, <shift>} |col 2=Move NOT value       |col 3 = Rd = {{l|not|{shifted Rm} }}}}
+{{inst|mn=MVN |col 1=MVN<cond>{S} Rd, Rm, {, <shift>} |col 2=Move NOT value       |col 3 = Rd = {{l|not|Shift(Rm) }}}}
-{{inst|cols=5|section=<span id="load_instructions">'''Load Instructions'''</span>}}
+{{inst|cols=5|section=<span id="load_instructions">'''Load Instructions'''</span><br><small>Load instructions move the content of memory addresses into registers.</small>}}
 {{inst|mn=LDM  |col 1=LDM<cond><type> Rn{!}, <reglist>{^} |col 2= Load multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Rd = [addr]<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;update address based on {type} }}
 {{inst|mn=LDR  |col 1=LDR<cond>{B} Rd, [Rn {, #imm}]{!}   |col 2=Load register immed |col 3 = Rd = [Rn + imm]<br>If !: Rn = Rn + imm}}
-{{inst|mn=LDR  |col 1=LDR<cond>{B} Rd,  [Rn, Rm {, <shift>}]{!}  |col 2=Load register     |col 3 = Rd = [Rn + {shifted Rm}]<br>If !: Rn = Rn + {shifted Rm}]}}
+{{inst|mn=LDR  |col 1=LDR<cond>{B} Rd,  [Rn, Rm {, <shift>}]{!}  |col 2=Load register     |col 3 = Rd = [Rn + Shift(Rm)]<br>If !: Rn = Rn + Shift(Rm)]}}
 {{inst|mn=LDR  |col 1=LDR<cond>{B}{T} Rd,  [Rn], #imm  |col 2=Load register, post index     |col 3 = Rd = [Rn]<br>Rn = Rn + imm}}
-{{inst|mn=LDR  |col 1=LDR<cond>{B}{T} Rd,  [Rn], Rm {, <shift>}  |col 2=Load register, post index     |col 3 = Rd = [Rn]<br>Rn = Rn + {shifted Rm} }}
+{{inst|mn=LDR  |col 1=LDR<cond>{B}{T} Rd,  [Rn], Rm {, <shift>}  |col 2=Load register, post index     |col 3 = Rd = [Rn]<br>Rn = Rn + Shift(Rm) }}
-{{inst|cols=5|section=<span id="store_instructions">'''Store Instructions'''</span>}}
+{{inst|cols=5|section=<span id="store_instructions">'''Store Instructions'''</span><br><small>Store instructions moves the values from registers into memory.</small>}}
 {{inst|mn=STM  |col 1=STM<cond><type> Rn{!}, <reglist>{^} |col 2= Store multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[addr] = Rd<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;update address based on {type} }}
 {{inst|mn=STR  |col 1=STR<cond>{B} Rd, [Rn {, #imm}]{!}   |col 2=Store register immed |col 3 = [Rn + imm] = Rd<br>If !: Rn = Rn + imm}}
-{{inst|mn=STR  |col 1=STR<cond>{B} Rd,  [Rn, Rm {, <shift>}]{!}  |col 2=Store register     |col 3 = [Rn + {shifted Rm}] = Rd<br>If !: Rn = Rn + {shifted Rm}]}}
+{{inst|mn=STR  |col 1=STR<cond>{B} Rd,  [Rn, Rm {, <shift>}]{!}  |col 2=Store register     |col 3 = [Rn + Shift(Rm)] = Rd<br>If !: Rn = Rn + Shift(Rm)]}}
 {{inst|mn=STR  |col 1=STR<cond>{B}{T} Rd,  [Rn], #imm  |col 2=Store register, post index     |col 3 = [Rn] = Rd<br>Rn = Rn + imm}}
-{{inst|mn=STR  |col 1=STR<cond>{B}{T} Rd,  [Rn], Rm {, <shift>}  |col 2=Store register, post index     |col 3 = [Rn] = Rd<br>Rn = Rn + {shifted Rm} }}
+{{inst|mn=STR  |col 1=STR<cond>{B}{T} Rd,  [Rn], Rm {, <shift>}  |col 2=Store register, post index     |col 3 = [Rn] = Rd<br>Rn = Rn + Shift(Rm) }}
-{{inst|cols=5|section=<span id="arithmetic_instructions">'''Arithmetic Instructions'''</span>}}
+{{inst|cols=5|section=<span id="arithmetic_instructions">'''Arithmetic Instructions'''</span><br><small>Arithmetic instructions perform basic mathematical operations on two operands.</small>}}
 {{inst|mn=ADC |col 1=ADC<cond>{S} Rd, Rn, #imm           |col 2=Add and carry immed               |col 3 =Rd = Rn + imm + C}}
-{{inst|mn=ADC |col 1=ADC<cond>{S} Rd, Rn, Rm{, <shift>}  |col 2=Add and carry                     |col 3 =Rd = Rn + {shifted Rm} + C}}
+{{inst|mn=ADC |col 1=ADC<cond>{S} Rd, Rn, Rm{, <shift>}  |col 2=Add and carry                     |col 3 =Rd = Rn + Shift(Rm) + C}}
 {{inst|mn=ADD |col 1=ADD<cond>S Rd, Rn, #imm             |col 2=Add immed                         |col 3 =Rd = Rn + imm}}
-{{inst|mn=ADD |col 1=ADD<cond>S Rd, Rn, Rm{, <shift>}    |col 2=Add                               |col 3 =Rd = Rn + {shifted Rm} }}
+{{inst|mn=ADD |col 1=ADD<cond>S Rd, Rn, Rm{, <shift>}    |col 2=Add                               |col 3 =Rd = Rn + Shift(Rm) }}
 {{inst|mn=RSB |col 1=RSB<cond>S Rd, Rn, #imm             |col 2=Reverse subtract immed            |col 3 =Rd = imm - Rn}}
-{{inst|mn=RSB |col 1=RSB<cond>S Rd, Rn, Rm{, <shift>}    |col 2=Reverse subtract                  |col 3 =Rd = {shifted Rm} - Rn }}
+{{inst|mn=RSB |col 1=RSB<cond>S Rd, Rn, Rm{, <shift>}    |col 2=Reverse subtract                  |col 3 =Rd = Shift(Rm) - Rn }}
 {{inst|mn=RSC |col 1=RSB<cond>S Rd, Rn, #imm             |col 2=Reverse subtract with carry immed |col 3 =Rd = imm - Rn - {{l|not|C}}}}
-{{inst|mn=RSC |col 1=RSB<cond>S Rd, Rn, Rm{, <shift>}    |col 2=Reverse subtract with carry       |col 3 =Rd = {shifted Rm} - Rn - {{l|not|C}}}}
+{{inst|mn=RSC |col 1=RSB<cond>S Rd, Rn, Rm{, <shift>}    |col 2=Reverse subtract with carry       |col 3 =Rd = Shift(Rm) - Rn - {{l|not|C}}}}
 {{inst|mn=SBC |col 1=SBC<cond>{S} Rd, Rn, #imm           |col 2=Subtract with carry immed         |col 3 =Rd = Rn - imm - {{l|not|C}}}}
-{{inst|mn=SBC |col 1=SBC<cond>{S} Rd, Rn, Rm{, <shift>}  |col 2=Subtract with carry               |col 3 =Rd = Rn - {shifted Rm} - {{l|not|C}}}}
+{{inst|mn=SBC |col 1=SBC<cond>{S} Rd, Rn, Rm{, <shift>}  |col 2=Subtract with carry               |col 3 =Rd = Rn - Shift(Rm) - {{l|not|C}}}}
 {{inst|mn=SUB |col 1=SUB<cond>{S} Rd, Rn, #imm           |col 2=Subtract immed                    |col 3 =Rd = Rn - imm}}
-{{inst|mn=SUB |col 1=SUB<cond>{S} Rd, Rn, Rm{, <shift>}  |col 2=Subtract                          |col 3 =Rd = Rn - {shifted Rm} }}
+{{inst|mn=SUB |col 1=SUB<cond>{S} Rd, Rn, Rm{, <shift>}  |col 2=Subtract                          |col 3 =Rd = Rn - Shift(Rm) }}
-{{inst|cols=5|section=<span id="logical_instructions">'''Logical Instructions'''</span>}}
+{{inst|cols=5|section=<span id="logical_instructions">'''Logical Instructions'''</span><br><small>Logical instructions perform logical bitwise operations on operands.</small>}}
 {{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, #imm          |col 2=AND immed          |col 3 =Rd = {{l|land2|Rn|imm}}}}
-{{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=AND                |col 3 =Rd = {{l|land2|Rn|{shifted Rm} }}}}
+{{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=AND                |col 3 =Rd = {{l|land2|Rn|Shift(Rm) }}}}
 {{inst|mn=BIC |col 1=BIC<cond>{S} Rd, Rn, #imm          |col 2=Bit clear immed    |col 3 =Rd = {{l|land2|Rn|{{l|not|imm}}}}}}
 {{inst|mn=BIC |col 1=BIC<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Bit clear          |col 3 =Rd = {{l|land2|Rn|{{l|not|Rm}}}}}}
 {{inst|mn=EOR |col 1=EOR<cond>{S} Rd, Rn, #imm          |col 2=Exclusive OR immed |col 3 =Rd = {{l|xor|Rn|imm}}}}
-{{inst|mn=EOR |col 1=EOR<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Exclusive OR       |col 3 =Rd = {{l|xor|Rn|{shifted Rm} }}}}
+{{inst|mn=EOR |col 1=EOR<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Exclusive OR       |col 3 =Rd = {{l|xor|Rn|Shift(Rm) }}}}
 {{inst|mn=ORR |col 1=ORR<cond>{S} Rd, Rn, #imm          |col 2=Logical OR immed   |col 3 =Rd = {{l|lor2|Rn|imm}}}}
-{{inst|mn=ORR |col 1=ORR<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Logical OR         |col 3 =Rd = {{l|lor2|Rn|{shifted Rm} }}}}
+{{inst|mn=ORR |col 1=ORR<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Logical OR         |col 3 =Rd = {{l|lor2|Rn|Shift(Rm) }}}}
-{{inst|cols=5|section=<span id="comparison_instructions">'''Comparison Instructions'''</span>}}
+{{inst|cols=5|section=<span id="comparison_instructions">'''Comparison Instructions'''</span><br><small>Comparison instructions compare two values and set appropriate status flags.</small>}}
 {{inst|mn=CMN   |col 1=CMN<cond> Rn, #imm          |col 2=Compare negative immed |col 3 =CPSR flags set on (Rn + imm)}}
-{{inst|mn=CMN   |col 1=CMN<cond> Rn, Rm{, <shift>} |col 2=Compare negative       |col 3 =CPSR flags set on (Rn + {shifted Rm})}}
+{{inst|mn=CMN   |col 1=CMN<cond> Rn, Rm{, <shift>} |col 2=Compare negative       |col 3 =CPSR flags set on (Rn + Shift(Rm))}}
 {{inst|mn=CMP   |col 1=CMP<cond> Rn, #imm          |col 2=Compare immed          |col 3 =CPSR flags set on (Rn - imm)}}
-{{inst|mn=CMP   |col 1=CMP<cond> Rn, Rm{, <shift>} |col 2=Compare                |col 3 =CPSR flags set on (Rn - {shifted Rm})}}
+{{inst|mn=CMP   |col 1=CMP<cond> Rn, Rm{, <shift>} |col 2=Compare                |col 3 =CPSR flags set on (Rn - Shift(Rm))}}
 {{inst|mn=TEQ   |col 1=TEQ<cond> Rn, #imm          |col 2=Test equality immed    |col 3 =CPSR flags set on ({{l|xor|Rn|imm}})}}
-{{inst|mn=TEQ   |col 1=TEQ<cond> Rn, Rm{, <shift>} |col 2=Test equality          |col 3 =CPSR flags set on ({{l|xor|Rn|{shifted Rm} }})}}
+{{inst|mn=TEQ   |col 1=TEQ<cond> Rn, Rm{, <shift>} |col 2=Test equality          |col 3 =CPSR flags set on ({{l|xor|Rn|Shift(Rm) }})}}
 {{inst|mn=TST   |col 1=TST<cond> Rn, #imm          |col 2=Test bits immed        |col 3 =CPSR flags set on ({{l|land2|Rn|imm}})}}
-{{inst|mn=TST   |col 1=TST<cond> Rn, Rm{, <shift>} |col 2=Test bits              |col 3 =CPSR flags set on ({{l|land2|Rn|{shifted Rm} }})}}
+{{inst|mn=TST   |col 1=TST<cond> Rn, Rm{, <shift>} |col 2=Test bits              |col 3 =CPSR flags set on ({{l|land2|Rn|Shift(Rm) }})}}
-{{inst|cols=5|section=<span id="branch_instructions">'''Branch Instructions'''</span>}}
+{{inst|cols=5|section=<span id="branch_instructions">'''Branch Instructions'''</span><br><small>Branch instructions order instruction processing to start elsewhere conditionally or unconditionally.</small>}}
 {{inst|mn=B  |col 1=B<cond> imm  |col 2=Branch relative |col 3 =PC = PC + address}}
 {{inst|mn=BL |col 1=BL<cond> imm |col 2=Branch and link relative |col 3 =LR = RET<br>PC = PC + address}}
-{{inst|cols=5|section=<span id="miscellaneous_instructions">'''Miscellaneous Instructions'''</span>}}
+{{inst|cols=5|section=<span id="miscellaneous_instructions">'''Miscellaneous Instructions'''</span><br><small>Any instruction that doesn't belong anywhere else.</small>}}
 {{inst|mn=SWI |col 1=SWI<cond> imm |col 2=Software interrupt |col 3 =LR = RET<br>Execute SWI vector in supervisor mode}}
 }}
+== Multiplication and Floating Point ==
+ARMv1 does not have support for multiplication. Software that requires multiplication will have to resort to a software implementation (e.g., [[Shift-and-Add Multiplication]]). This was considerably slow and was consequently added in later ARM versions. Likewise there was no support for hardware floating point or an ability to do such operations on an external FPU coprocessor.
+== Exception Vector Map ==
+{| class="wikitable"
+|-
+! Address !! Function !! Priority
+|-
+| 000 0000 || Reset || 0
+|-
+| 000 0004 || Undefined Instruction Trap || 6
+|-
+| 000 0008 || Software Interrupt || 7
+|-
+| 000 000C || Abort (Prefetch) || 5
+|-
+| 000 0010 || Abort (Data) || 2
+|-
+| 000 0014 || Address Exception || 1
+|-
+| 000 0018 || Normal Interrupt (IRQ) || 4
+|-
+| 000 001C || Fast Interrupt (FIRQ) || 3

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