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Difference between revisions of "amd/athlon mp/amp1900dms3c"
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Latest revision as of 15:20, 13 December 2017
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AMD Athlon MP 1900+ | |||||||||||
General Info | |||||||||||
Designer | AMD | ||||||||||
Manufacturer | AMD | ||||||||||
Model Number | Athlon MP 1900+ | ||||||||||
Part Number | AMP1900DMS3C | ||||||||||
Market | Server | ||||||||||
Introduction | December 12, 2001 (announced) December 12, 2001 (launched) | ||||||||||
Release Price | $319 | ||||||||||
Shop | Amazon | ||||||||||
General Specs | |||||||||||
Family | Athlon MP | ||||||||||
Locked | Yes | ||||||||||
Frequency | 1,600 MHz | ||||||||||
Bus type | FSB | ||||||||||
Bus speed | 133 MHz | ||||||||||
Bus rate | 266 MT/s | ||||||||||
Clock multiplier | 12 | ||||||||||
CPUID | 662 | ||||||||||
Microarchitecture | |||||||||||
Microarchitecture | K7 | ||||||||||
Platform | Athlon MP | ||||||||||
Chipset | AMD-760MP | ||||||||||
Core Name | Palomino | ||||||||||
Core Family | 6 | ||||||||||
Core Model | 6 | ||||||||||
Core Stepping | 2 | ||||||||||
Process | 180 nm | ||||||||||
Transistors | 37,500,000 | ||||||||||
Technology | CMOS | ||||||||||
Die | 128 mm² | ||||||||||
Word Size | 32 bit | ||||||||||
Cores | 1 | ||||||||||
Threads | 1 | ||||||||||
Max Memory | 4 GiB | ||||||||||
Multiprocessing | |||||||||||
Max SMP | 2-Way (Multiprocessor) | ||||||||||
Electrical | |||||||||||
Vcore | 1.75 V | ||||||||||
TDP | 66 W | ||||||||||
TDP (Typical) | 58.9 W | ||||||||||
Tjunction | 0 °C – 95 °C | ||||||||||
Tcase | 0 °C – 95 °C | ||||||||||
Tstorage | -40 °C – 100 °C | ||||||||||
Packaging | |||||||||||
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The Athlon MP 1900+ (OPN AMP1900DMS3C) based on the Palomino core was a 32-bit x86 multiprocessor developed by AMD and introduced in late 2001 for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12 multiplier). This processor, which was based on the K7 microarchitecture, was manufactured on a mature 180 nm copper interconnect technology at AMD's Fab 30 in Dresden, Germany.
Cache[edit]
- Main article: K7 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics[edit]
This MPU has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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- Advanced Configuration and Power Interface
- Halt State
- Stop Grant State
Documents[edit]
Datasheets[edit]
- AMD Athlon MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms; Publication # 25480 Rev: D; Issue Date: June 2002.
Others[edit]
- System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors; Publication # 25325; Rev: B; August 2002.
Facts about "Athlon MP 1900+ - AMD"
has amd smartmp technology | true + |
has feature | SmartMP Technology +, ACPI +, Halt State + and Stop Grant State + |
has multiprocessing support | true + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 2-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |