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{{dec title|Process Technology}}
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{{dec title|Process Technology History}}
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This article details details '''[[DEC]]'s [[Semiconductor Process Technology]]''' history for research and posterity.
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This article details details '''[[DEC]]'s [[semiconductor process technology]]''' history for research and posterity.
  
 
The table below shows the history of DEC's process scaling. Values were taken from various DEC documents including historical presentations and journals, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between DEC's own documents and therefore discrepancies may exist.
 
The table below shows the history of DEC's process scaling. Values were taken from various DEC documents including historical presentations and journals, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between DEC's own documents and therefore discrepancies may exist.
  
 
== Timeline ==
 
== Timeline ==
 +
High-performance CMOS process started at Digital's Hudson, Massachusetts foundry in the mid-1980s along with Digital's new CMOS VLSI microprocessor designs. Digital adopted a similar manufacturing strategy to Intel whereby scaling of feature sizes occurs along with their development of new generations of high-performance microprocessors. Digital continued to operate the Hudson fab until 1997.Fab-6 in Hudson, Mass was sold to [[Intel]] which consequently upgraded it for $800M to Intel's propiatery [[0.18 µm]] (see {{intel|Process|Intel's Process}}). Intel continued to operate the fab until late 2013 when they announced that it will be closing the Hudson Fab due to no longer meeting their requirements such as aging technology.
 +
 
<div style="overflow-x: auto;" class="scrollable">
 
<div style="overflow-x: auto;" class="scrollable">
 
<table class="wikitable" style="text-align: center;">
 
<table class="wikitable" style="text-align: center;">
 
<tr><th>Year</th><th>Process</th><th>[[technology node|Node]]</th><th>MLayers</th><th>µarchs</th><th colspan="4">Attributes</th></tr>
 
<tr><th>Year</th><th>Process</th><th>[[technology node|Node]]</th><th>MLayers</th><th>µarchs</th><th colspan="4">Attributes</th></tr>
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{{dec proc tech |year= |name=ZMOS |mlayers=2 |node=3 µm
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{{dec proc tech |year=1984 |name=ZMOS |mlayers=2 |node=3 µm
 
   |archs=V-11, MicroVAX II
 
   |archs=V-11, MicroVAX II
 
   |a1=T<sub>ox</sub>        |d1=43 nm
 
   |a1=T<sub>ox</sub>        |d1=43 nm
 +
  |a2=L<sub>g</sub>          |d2=3 µm
 
}}
 
}}
−
{{dec proc tech |year= |name=CMOS-1 |mlayers= |node=2 µm
+
{{dec proc tech |year=1986 |name=CMOS-1 |mlayers=2 |node=2 µm
−
   |archs=
+
   |archs=CVAX
−
   |a1=T<sub>ox</sub>        |d1=
+
   |a1=T<sub>ox</sub>        |d1=30 nm  |a12=Masks    |d12=12
 +
  |a2=V<sub>dd</sub>        |d2=5 V
 +
  |a3=L<sub>g</sub>          |d3=2 µm
 
}}
 
}}
−
{{dec proc tech |year= |name=CMOS-2 |mlayers= |node=1.5 µm
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{{dec proc tech |year=1988 |name=CMOS-2 |mlayers=2 |node=1.5 µm
−
   |archs=
+
   |archs=CVAX+, Rigel
−
   |a1=T<sub>ox</sub>        |d1=
+
   |a1=T<sub>ox</sub>        |d1=22.5 nm  |a12=Masks    |d12=13
 +
  |a2=V<sub>dd</sub>        |d2=5 V
 +
  |a3=L<sub>g</sub>          |d3=1.5 µm 
 
}}
 
}}
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{{dec proc tech |year= |name=CMOS-3 |mlayers= |node=1 µm
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{{dec proc tech |year=1990 |name=CMOS-3 |mlayers=2 |node=1 µm
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   |archs=
+
   |archs=Mariah
−
   |a1=T<sub>ox</sub>        |d1=
+
   |a1=T<sub>ox</sub>        |d1=15 nm  |a12=Masks    |d12=20
 +
  |a2=V<sub>dd</sub>        |d2=3.3 V
 +
  |a3=L<sub>g</sub>          |d3=1 µm   
 
}}
 
}}
 
{{dec proc tech |year=1991 |name=CMOS-4 |mlayers=3 |node=0.75 µm
 
{{dec proc tech |year=1991 |name=CMOS-4 |mlayers=3 |node=0.75 µm
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   |archs=NVAX, Alpha 21064
+
   |archs=Alpha 21064, NVAX
−
   |a1=T<sub>ox</sub>        |d1=10.5 nm
+
   |a1=T<sub>ox</sub>        |d1=10.5 nm     |a12=Masks          |d12=21
−
   |a2=V<sub>dd</sub> |d2=3.3 V      |a22=SRAM            |d22= 100 µm²
+
   |a2=V<sub>dd</sub>         |d2=3.3 V      |a22=SRAM            |d22= 100 µm²
−
   |a3=L<sub>g</sub> |d3=0.75 µm    |a32=L<sub>eff</sub> |d32=0.50 µm
+
   |a3=L<sub>g</sub>         |d3=0.75 µm    |a32=L<sub>eff</sub> |d32=0.50 µm
 
}}
 
}}
−
{{dec proc tech |year= |name=CMOS-4S |mlayers=3 |node=0.675 µm
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{{dec proc tech |year=1996 |name=CMOS-4S |mlayers=3 |node=0.675 µm
−
   |archs=
+
   |archs=NVAX, NVAX+, SOC
 
   |a1=T<sub>ox</sub>        |d1=
 
   |a1=T<sub>ox</sub>        |d1=
 +
  |a2=L<sub>g</sub>          |d2=0.675 µm 
 
}}
 
}}
−
{{dec proc tech |year=1994 |name=CMOS-5 |mlayers=4 |node=0.5 µm
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{{dec proc tech |year=1994 |name=CMOS-5 |mlayers=4 |node=0.50 µm
−
   |archs=
+
   |archs=Alpha 21164, NVAX++
−
   |a1=T<sub>ox</sub>        |d1=
+
   |a1=T<sub>ox</sub>        |d1=9 nm
 +
  |a2=V<sub>dd</sub>        |d2=3.3 V
 +
  |a3=L<sub>g</sub>          |d3=0.50 µm    |a32=L<sub>eff</sub> |d32=0.365 µm
 
}}
 
}}
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{{dec proc tech |year= |name=CMOS-6 |mlayers=4 |node=0.35 µm
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{{dec proc tech |year=1996 |name=CMOS-6 |mlayers=4 |node=0.35 µm
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   |archs=
+
   |archs=Alpha 21264, StrongARM
−
   |a1=T<sub>ox</sub>        |d1=
+
   |a1=T<sub>ox</sub>        |d1=6 nm
 +
  |a2=L<sub>g</sub>          |d2=0.35 µm    |a22=L<sub>eff</sub> |d22=0.25 µm
 
}}
 
}}
−
{{dec proc tech |year=1997 |name=CMOS-7 |mlayers= |node=0.25 µm
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{{dec proc tech |year=1997 |name=CMOS-7 |mlayers=5 |node=0.25 µm
 
   |archs=
 
   |archs=
 
   |a1=T<sub>ox</sub>        |d1=
 
   |a1=T<sub>ox</sub>        |d1=
 
}}
 
}}
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<tr><td>1997</td><td colspan="8">Fab-6 in Hudson, Mass was sold to [[Intel]] which consequently upgraded it for $800M to Intel's propiatery [[0.18 µm]] (see {{intel|Process|Intel's Process}}).</td></tr>
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<tr><td>1997</td><td colspan="8" style="text-align: left;">Changed ownership to Intel (see {{intel|Process|Intel's Process}})</td></tr>
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<tr><td>2013</td><td colspan="8">In late 2013 Intel announced that it will be closing the Hudson Fab due to no longer meeting their requirements such as aging technology.</td></tr>
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<tr><td>2013</td><td colspan="8" style="text-align: left;">Intel announced that it will be closing the Hudson Fab due to dated technology.</td></tr>
 
</table>
 
</table>
 
</div>
 
</div>
  
−
<!--
+
Additionally, DEC fabricated on Motorola's [[ECL]] process:
−
    |a12=Gate Dielectric |d12=SiO<sub>2</sub>
+
 
−
  |a2=V<sub>dd</sub> |d2=5 V      |a22=SRAM            |d22= 1120 µm²
+
{| class="wikitable"
−
  |a3=L<sub>g</sub>  |d3=3.0 µm
+
|-
−
  |a4=CPP            |d4=7 µm      |a42=MMP            |d42=
+
| Mosaic1 || 3 µm ECL
−
-->
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|-
 +
| Mosaic2 || 1 µm ECL
 +
|-
 +
| Mosaic3 ||
 +
|}
 +
 
 +
== Other processes ==
 +
{{other processes list}}

Latest revision as of 23:02, 25 December 2017

This article details details DEC's semiconductor process technology history for research and posterity.

The table below shows the history of DEC's process scaling. Values were taken from various DEC documents including historical presentations and journals, ISSCC papers, and IEDM papers. Note that while a great deal of effort was put into ensuring the accuracy of the values, some numbers vary to a small degree between DEC's own documents and therefore discrepancies may exist.

Timeline[edit]

High-performance CMOS process started at Digital's Hudson, Massachusetts foundry in the mid-1980s along with Digital's new CMOS VLSI microprocessor designs. Digital adopted a similar manufacturing strategy to Intel whereby scaling of feature sizes occurs along with their development of new generations of high-performance microprocessors. Digital continued to operate the Hudson fab until 1997.Fab-6 in Hudson, Mass was sold to Intel which consequently upgraded it for $800M to Intel's propiatery 0.18 µm (see Intel's Process). Intel continued to operate the fab until late 2013 when they announced that it will be closing the Hudson Fab due to no longer meeting their requirements such as aging technology.

YearProcessNodeMLayersµarchsAttributes
1984 ZMOS 3 µm 2 V-11,
MicroVAX II		Tox43 nm
Lg3 µm
1986 CMOS-1 2 µm 2 CVAXTox30 nmMasks12
Vdd5 V
Lg2 µm
1988 CMOS-2 1.5 µm 2 CVAX+,
Rigel		Tox22.5 nmMasks13
Vdd5 V
Lg1.5 µm
1990 CMOS-3 1 µm 2 MariahTox15 nmMasks20
Vdd3.3 V
Lg1 µm
1991 CMOS-4 0.75 µm 3 Alpha 21064,
NVAX		Tox10.5 nmMasks21
Vdd3.3 VSRAM100 µm²
Lg0.75 µmLeff0.50 µm
1996 CMOS-4S 0.675 µm 3 NVAX,
NVAX+,
SOC		Tox
Lg0.675 µm
1994 CMOS-5 0.50 µm 4 Alpha 21164,
NVAX++		Tox9 nm
Vdd3.3 V
Lg0.50 µmLeff0.365 µm
1996 CMOS-6 0.35 µm 4 Alpha 21264,
StrongARM		Tox6 nm
Lg0.35 µmLeff0.25 µm
1997 CMOS-7 0.25 µm 5 Tox
1997Changed ownership to Intel (see Intel's Process)
2013Intel announced that it will be closing the Hudson Fab due to dated technology.

Additionally, DEC fabricated on Motorola's ECL process:

Mosaic1 3 µm ECL
Mosaic2 1 µm ECL
Mosaic3

Other processes[edit]

Semiconductor Process history by company:

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