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Difference between revisions of "intel/xeon gold/6136"
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{{intel title|Xeon Gold 6136}} | {{intel title|Xeon Gold 6136}} | ||
− | {{ | + | {{chip |
− | + | |name=Xeon Gold 6136 | |
− | | name | + | |image=skylake sp (basic).png |
− | + | |designer=Intel | |
− | + | |manufacturer=Intel | |
− | | image | + | |model number=6136 |
− | + | |part number=CD8067303405800 | |
− | | designer | + | |s-spec=SR3B2 |
− | | manufacturer | + | |s-spec qs=QMRX |
− | | model number | + | |market=Server |
− | | part number | + | |first announced=April 25, 2017 |
− | + | |first launched=July 11, 2017 | |
− | + | |release price=$2460.00 | |
− | | s-spec | + | |family=Xeon Gold |
− | | s-spec | + | |series=6100 |
− | | market | + | |locked=Yes |
− | | first announced | + | |frequency=3,000 MHz |
− | | first launched | + | |turbo frequency1=3,700 MHz |
− | | | + | |bus type=DMI 3.0 |
− | | | + | |bus links=4 |
− | | | + | |bus rate=8 GT/s |
+ | |clock multiplier=30 | ||
+ | |cpuid=0x50654 | ||
+ | |isa=x86-64 | ||
+ | |isa family=x86 | ||
+ | |microarch=Skylake (server) | ||
+ | |platform=Purley | ||
+ | |chipset=Lewisburg | ||
+ | |core name=Skylake SP | ||
+ | |core family=6 | ||
+ | |core stepping=H0 | ||
+ | |process=14 nm | ||
+ | |technology=CMOS | ||
+ | |word size=64 bit | ||
+ | |core count=12 | ||
+ | |thread count=24 | ||
+ | |max memory=768 GiB | ||
+ | |max cpus=4 | ||
+ | |smp interconnect=UPI | ||
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
+ | |tdp=150 W | ||
+ | |tcase min=0 °C | ||
+ | |tcase max=85 °C | ||
+ | |dts min=0 °C | ||
+ | |dts max=103 °C | ||
+ | |package name 1=intel,fclga_3647 | ||
+ | }} | ||
+ | '''Xeon Gold 6136''' is a {{arch|64}} [[dodeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6136, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3 GHz with a TDP of 150 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory. | ||
− | + | == Cache == | |
− | | | + | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} |
− | | | + | The Xeon Gold 6136 features a considerably larger non-default 24.75 MiB of [[L3]], a size that would normally be found on an 18-core part. |
− | + | {{cache size | |
− | | | + | |l1 cache=768 KiB |
− | | | + | |l1i cache=384 KiB |
− | | | + | |l1i break=12x32 KiB |
− | | | + | |l1i desc=8-way set associative |
− | | | + | |l1d cache=384 KiB |
− | | | + | |l1d break=12x32 KiB |
− | | | + | |l1d desc=8-way set associative |
− | | | + | |l1d policy=write-back |
− | | | + | |l2 cache=12 MiB |
− | | | + | |l2 break=12x1 MiB |
− | | | + | |l2 desc=16-way set associative |
− | | | + | |l2 policy=write-back |
− | | | + | |l3 cache=24.75 MiB |
− | | | + | |l3 break=18x1.375 MiB |
− | | | + | |l3 desc=11-way set associative |
− | | | + | |l3 policy=write-back |
+ | }} | ||
− | + | == Memory controller == | |
− | + | {{memory controller | |
− | + | |type=DDR4-2666 | |
− | + | |ecc=Yes | |
− | + | |max mem=768 GiB | |
− | + | |controllers=2 | |
− | + | |channels=6 | |
− | | | + | |max bandwidth=119.21 GiB/s |
− | + | |bandwidth schan=19.87 GiB/s | |
− | + | |bandwidth dchan=39.74 GiB/s | |
− | + | |bandwidth qchan=79.47 GiB/s | |
− | + | |bandwidth hchan=119.21 GiB/s | |
− | + | }} | |
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− | + | == Expansions == | |
− | + | {{expansions | |
− | + | | pcie revision = 3.0 | |
− | + | | pcie lanes = 48 | |
− | + | | pcie config = x16 | |
− | + | | pcie config 2 = x8 | |
− | | | + | | pcie config 3 = x4 |
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}} | }} | ||
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== Features == | == Features == | ||
Line 134: | Line 116: | ||
|avx=Yes | |avx=Yes | ||
|avx2=Yes | |avx2=Yes | ||
− | | | + | |avx512f=Yes |
+ | |avx512cd=Yes | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No | ||
Line 149: | Line 142: | ||
|f16c=Yes | |f16c=Yes | ||
|tbt1=No | |tbt1=No | ||
− | |tbt2= | + | |tbt2=Yes |
|tbmt3=No | |tbmt3=No | ||
|bpt=No | |bpt=No | ||
|eist=Yes | |eist=Yes | ||
− | |sst= | + | |sst=Yes |
|flex=No | |flex=No | ||
|fastmem=No | |fastmem=No | ||
+ | |ivmd=Yes | ||
+ | |intelnodecontroller=Yes | ||
+ | |intelnode=Yes | ||
+ | |kpt=Yes | ||
+ | |ptt=Yes | ||
+ | |intelrunsure=Yes | ||
+ | |mbe=Yes | ||
|isrt=No | |isrt=No | ||
|sba=No | |sba=No | ||
Line 163: | Line 163: | ||
|ipt=No | |ipt=No | ||
|tsx=Yes | |tsx=Yes | ||
− | |txt= | + | |txt=Yes |
|ht=Yes | |ht=Yes | ||
|vpro=Yes | |vpro=Yes | ||
Line 169: | Line 169: | ||
|vtd=Yes | |vtd=Yes | ||
|ept=Yes | |ept=Yes | ||
− | |mpx= | + | |mpx=No |
|sgx=No | |sgx=No | ||
|securekey=No | |securekey=No | ||
− | |osguard= | + | |osguard=No |
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
Line 179: | Line 179: | ||
|amdvi=No | |amdvi=No | ||
|amdv=No | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
|rvi=No | |rvi=No | ||
|smt=No | |smt=No | ||
Line 184: | Line 187: | ||
|xfr=No | |xfr=No | ||
}} | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=3,000 MHz | ||
+ | |freq_1=3,700 MHz | ||
+ | |freq_2=3,700 MHz | ||
+ | |freq_3=3,600 MHz | ||
+ | |freq_4=3,600 MHz | ||
+ | |freq_5=3,600 MHz | ||
+ | |freq_6=3,600 MHz | ||
+ | |freq_7=3,600 MHz | ||
+ | |freq_8=3,600 MHz | ||
+ | |freq_9=3,600 MHz | ||
+ | |freq_10=3,600 MHz | ||
+ | |freq_11=3,600 MHz | ||
+ | |freq_12=3,600 MHz | ||
+ | |freq_avx2_base=2,600 MHz | ||
+ | |freq_avx2_1=3,600 MHz | ||
+ | |freq_avx2_2=3,600 MHz | ||
+ | |freq_avx2_3=3,400 MHz | ||
+ | |freq_avx2_4=3,400 MHz | ||
+ | |freq_avx2_5=3,300 MHz | ||
+ | |freq_avx2_6=3,300 MHz | ||
+ | |freq_avx2_7=3,300 MHz | ||
+ | |freq_avx2_8=3,300 MHz | ||
+ | |freq_avx2_9=3,300 MHz | ||
+ | |freq_avx2_10=3,300 MHz | ||
+ | |freq_avx2_11=3,300 MHz | ||
+ | |freq_avx2_12=3,300 MHz | ||
+ | |freq_avx512_base=2,100 MHz | ||
+ | |freq_avx512_1=3,500 MHz | ||
+ | |freq_avx512_2=3,500 MHz | ||
+ | |freq_avx512_3=3,300 MHz | ||
+ | |freq_avx512_4=3,300 MHz | ||
+ | |freq_avx512_5=3,100 MHz | ||
+ | |freq_avx512_6=3,100 MHz | ||
+ | |freq_avx512_7=3,100 MHz | ||
+ | |freq_avx512_8=3,100 MHz | ||
+ | |freq_avx512_9=2,700 MHz | ||
+ | |freq_avx512_10=2,700 MHz | ||
+ | |freq_avx512_11=2,700 MHz | ||
+ | |freq_avx512_12=2,700 MHz | ||
+ | }} | ||
+ | |||
+ | == Benchmarks == | ||
+ | {{benchmarks main | ||
+ | | | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00145.html|test_timestamp=2017-10-07 20:52:23-0400|chip_count=2|core_count=24|copies_count=48|vendor=HPE|system=ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)|SPECrate2017_fp_base=159|SPECrate2017_fp_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00149.html|test_timestamp=2017-10-13 04:45:58-0400|chip_count=2|core_count=24|thread_count=24|vendor=HPE|system=ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)|SPECspeed2017_fp_base=103|SPECspeed2017_fp_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00155.html|test_timestamp=2017-10-13 05:57:20-0400|chip_count=2|core_count=24|thread_count=24|vendor=HPE|system=ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)|SPECspeed2017_int_base=8.8|SPECspeed2017_int_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00206.html|test_timestamp=2017-10-07 16:38:18-0400|chip_count=2|core_count=24|copies_count=48|vendor=HPE|system=ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)|SPECrate2017_int_base=149|SPECrate2017_int_peak=}} | ||
+ | }} | ||
+ | |||
+ | [[Category:microprocessor models by intel based on skylake extreme core count die]] |
Latest revision as of 01:20, 29 December 2019
Edit Values | |
Xeon Gold 6136 | |
![]() | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 6136 |
Part Number | CD8067303405800 |
S-Spec | SR3B2 QMRX (QS) |
Market | Server |
Introduction | April 25, 2017 (announced) July 11, 2017 (launched) |
Release Price | $2460.00 |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6100 |
Locked | Yes |
Frequency | 3,000 MHz |
Turbo Frequency | 3,700 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 30 |
CPUID | 0x50654 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | H0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 12 |
Threads | 24 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 150 W |
Tcase | 0 °C – 85 °C |
TDTS | 0 °C – 103 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Xeon Gold 6136 is a 64-bit dodeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6136, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3 GHz with a TDP of 150 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Cache[edit]
- Main article: Skylake § Cache
The Xeon Gold 6136 features a considerably larger non-default 24.75 MiB of L3, a size that would normally be found on an 18-core part.
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | ||
Normal | 3,000 MHz | 3,700 MHz | 3,700 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz |
AVX2 | 2,600 MHz | 3,600 MHz | 3,600 MHz | 3,400 MHz | 3,400 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz |
AVX512 | 2,100 MHz | 3,500 MHz | 3,500 MHz | 3,300 MHz | 3,300 MHz | 3,100 MHz | 3,100 MHz | 3,100 MHz | 3,100 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz |
Benchmarks[edit]
Test: SPEC CPU2017
Tested: 2017-10-07 20:52:23-0400
Chips: 2, Cores: 24, Copies: 48
Vendor: HPE
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
Tested: 2017-10-07 20:52:23-0400
Chips: 2, Cores: 24, Copies: 48
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
SPECrate2017_fp_base: 159
Test: SPEC CPU2017
Tested: 2017-10-13 04:45:58-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: HPE
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
Tested: 2017-10-13 04:45:58-0400
Chips: 2, Cores: 24, Threads: 24
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
SPECspeed2017_fp_base: 103
Test: SPEC CPU2017
Tested: 2017-10-13 05:57:20-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: HPE
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
Tested: 2017-10-13 05:57:20-0400
Chips: 2, Cores: 24, Threads: 24
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
SPECspeed2017_int_base: 8.8
Test: SPEC CPU2017
Tested: 2017-10-07 16:38:18-0400
Chips: 2, Cores: 24, Copies: 48
Vendor: HPE
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
Tested: 2017-10-07 16:38:18-0400
Chips: 2, Cores: 24, Copies: 48
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
SPECrate2017_int_base: 149
Facts about "Xeon Gold 6136 - Intel"
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions + and OS Guard + |
has intel enhanced speedstep technology | true + |
has intel supervisor mode execution protection | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
x86/has memory protection extensions | true + |