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Difference between revisions of "intel/xeon platinum/8176m"
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{{intel title|Xeon Platinum 8176M}}
 
{{intel title|Xeon Platinum 8176M}}
−
{{mpu
+
{{chip
−
| future              = Yes
+
|name=Xeon Platinum 8176M
−
| name               = Xeon Platinum 8176M
+
|image=skylake sp (basic).png
−
| no image            = Yes
+
|designer=Intel
−
| image              =
+
|manufacturer=Intel
−
| image size          =
+
|model number=8176M
−
| caption            =  
+
|part number=CD8067303133605
−
| designer           = Intel
+
|s-spec=SR37U
−
| manufacturer       = Intel
+
|s-spec qs=QM7R
−
| model number       = 8176M
+
|market=Server
−
| part number         = CD8067303133605
+
|first announced=April 25, 2017
−
| part number 1      =
+
|first launched=July 11, 2017
−
| part number 2      =
+
|release price=$11722.00
−
| s-spec             = SR37U
+
|family=Xeon Platinum
−
| s-spec 2            =  
+
|series=8000
−
| market             = Server
+
|frequency=2,100 MHz
−
| first announced     = April 25, 2017
+
|turbo frequency1=3,800 MHz
−
| first launched     =  
+
|clock multiplier=21
−
| last order          =  
+
|cpuid=0x50654
−
| last shipment      =  
+
|isa=x86-64
−
| release price      =  
+
|isa family=x86
 +
|microarch=Skylake (server)
 +
|platform=Purley
 +
|chipset=Lewisburg
 +
|core name=Skylake SP
 +
|core family=6
 +
|core stepping=H0
 +
|process=14 nm
 +
|technology=CMOS
 +
|word size=64 bit
 +
|core count=28
 +
|thread count=56
 +
|max memory=1,536 GiB
 +
|max cpus=8
 +
|smp interconnect=UPI
 +
|smp interconnect links=3
 +
|smp interconnect rate=10.4 GT/s
 +
|tdp=165 W
 +
|tcase min=0 °C
 +
|tcase max=89 °C
 +
|dts min=0 °C
 +
|dts max=97 °C
 +
|package name 1=intel,fclga_3647
 +
|successor=Xeon Platinum 8276M
 +
|successor link=intel/xeon_platinum/8276m
 +
}}
 +
'''Xeon Platinum 8176M''' is a {{arch|64}} [[28-core]] [[x86]] multi-socket highest performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8176M, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 165 W and a {{intel|turbo boost}} frequency of up to 3.8 GHz, supports up 1.5 TiB of hexa-channel DDR4-2666 ECC memory.
  
−
| family              = Xeon Platinum
+
As indicated by the ''M'' suffix, this specific model supports double the memory capacity for up to 1.5 TiB per socket.
−
| series              = 8100
 
−
| locked              = Yes
 
−
| frequency          = 2.1 GHz
 
−
| turbo frequency    =
 
−
| turbo frequency1    =
 
−
| turbo frequency2    =
 
−
| turbo frequency3    =
 
−
| turbo frequency4    =
 
−
| turbo frequency5    =
 
−
| turbo frequency6    =
 
−
| turbo frequency7    =
 
−
| turbo frequency8    =
 
−
| bus type            = DMI 3.0
 
−
| bus speed          =
 
−
| bus rate            = 8 GT/s
 
−
| bus links          = 4
 
−
| clock multiplier    = 21
 
−
| cpuid              =
 
−
| cpuid 2            =
 
  
−
| isa family          = x86-64
+
== Cache ==
−
| isa                = x86
+
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
−
| microarch          = Skylake
+
{{cache size
−
| platform            = Purley
+
|l1 cache=1.75 MiB
−
| chipset            = Lewisburg
+
|l1i cache=896 KiB
−
| core name          = Skylake SP
+
|l1i break=28x32 KiB
−
| core family        =  
+
|l1i desc=8-way set associative
−
| core model          =  
+
|l1d cache=896 KiB
−
| core stepping      = H0
+
|l1d break=28x32 KiB
−
| process            = 14 nm
+
|l1d desc=8-way set associative
−
| transistors        =  
+
|l1d policy=write-back
−
| technology          = CMOS
+
|l2 cache=28 MiB
−
| die area            = <!-- XX mm² -->
+
|l2 break=28x1 MiB
−
| die width          =  
+
|l2 desc=16-way set associative
−
| die length          =  
+
|l2 policy=write-back
−
| word size          = 64 bit
+
|l3 cache=38.5 MiB
−
| core count          =  
+
|l3 break=28x1.375 MiB
−
| thread count        =  
+
|l3 desc=11-way set associative
−
| max cpus            = 8
+
|l3 policy=write-back
−
| max memory          =
+
}}
  
−
| electrical          =  
+
== Memory controller ==
−
| power              =  
+
{{memory controller
−
| average power      =  
+
|type=DDR4-2666
−
| idle power          =  
+
|ecc=Yes
−
| v core              =
+
|max mem=1,536 GiB
−
| v core tolerance    = <!-- OR ... -->
+
|controllers=2
−
| v core min          =  
+
|channels=6
−
| v core max         =  
+
|max bandwidth=119.21 GiB/s
−
| v io                =  
+
|bandwidth schan=19.87 GiB/s
−
| v io tolerance      =  
+
|bandwidth dchan=39.74 GiB/s
−
| v io 2              = <!-- OR ... -->
+
|bandwidth qchan=79.47 GiB/s
−
| v io 3              =  
+
|bandwidth hchan=119.21 GiB/s
−
| sdp                =  
+
}}
−
| tdp                =  
 
−
| tdp typical        =
 
−
| ctdp down          =
 
−
| ctdp down frequency =
 
−
| ctdp up            =
 
−
| ctdp up frequency  =
 
−
| temp min            = <!-- use TJ/TC whenever possible instead -->
 
−
| temp max            =
 
−
| tjunc min          = <!-- .. °C -->
 
−
| tjunc max          =
 
−
| tcase min          =
 
−
| tcase max          =
 
−
| tstorage min        =
 
−
| tstorage max        =
 
−
| tambient min        =
 
−
| tambient max        =
 
  
−
| package module 1    =  
+
== Expansions ==
−
| package module 2    =  
+
{{expansions
−
<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
+
| pcie revision     = 3.0
−
| packaging          = Yes
+
| pcie lanes        = 48
−
| package 0          = FCLGA-3647
+
| pcie config        = x16
−
| package 0 type      = LGA
+
| pcie config 2      = x8
−
| package 0 pins     = 3647
+
| pcie config 3      = x4
−
| package 0 pitch    =
 
−
| package 0 width    =  
 
−
| package 0 length    =  
 
−
| package 0 height    =  
 
−
| socket 0            = LGA-3647
 
−
| socket 0 type      = LGA
 
 
}}
 
}}
−
'''Xeon Platinum 8176M''' is a {{arch|64}} [[x86]] high-performance server [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 8176M operates at 2.1 GHz.
 
−
 
−
 
−
{{unknown features}}
 
  
 
== Features ==  
 
== Features ==  
Line 134: Line 115:
 
|avx=Yes
 
|avx=Yes
 
|avx2=Yes
 
|avx2=Yes
−
|avx512=Yes
+
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 
|abm=Yes
 
|abm=Yes
 
|tbm=No
 
|tbm=No
Line 149: Line 141:
 
|f16c=Yes
 
|f16c=Yes
 
|tbt1=No
 
|tbt1=No
−
|tbt2=No
+
|tbt2=Yes
 
|tbmt3=No
 
|tbmt3=No
 
|bpt=No
 
|bpt=No
 
|eist=Yes
 
|eist=Yes
−
|sst=No
+
|sst=Yes
 
|flex=No
 
|flex=No
 
|fastmem=No
 
|fastmem=No
 +
|ivmd=Yes
 +
|intelnodecontroller=Yes
 +
|intelnode=Yes
 +
|kpt=Yes
 +
|ptt=Yes
 +
|intelrunsure=Yes
 +
|mbe=Yes
 
|isrt=No
 
|isrt=No
 
|sba=No
 
|sba=No
Line 163: Line 162:
 
|ipt=No
 
|ipt=No
 
|tsx=Yes
 
|tsx=Yes
−
|txt=No
+
|txt=Yes
 
|ht=Yes
 
|ht=Yes
 
|vpro=Yes
 
|vpro=Yes
Line 169: Line 168:
 
|vtd=Yes
 
|vtd=Yes
 
|ept=Yes
 
|ept=Yes
−
|mpx=Yes
+
|mpx=No
 
|sgx=No
 
|sgx=No
 
|securekey=No
 
|securekey=No
−
|osguard=Yes
+
|osguard=No
 
|3dnow=No
 
|3dnow=No
 
|e3dnow=No
 
|e3dnow=No
Line 179: Line 178:
 
|amdvi=No
 
|amdvi=No
 
|amdv=No
 
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 
|rvi=No
 
|rvi=No
 
|smt=No
 
|smt=No
Line 184: Line 186:
 
|xfr=No
 
|xfr=No
 
}}
 
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=2,100 MHz
 +
|freq_1=3,800 MHz
 +
|freq_2=3,800 MHz
 +
|freq_3=3,600 MHz
 +
|freq_4=3,600 MHz
 +
|freq_5=3,500 MHz
 +
|freq_6=3,500 MHz
 +
|freq_7=3,500 MHz
 +
|freq_8=3,500 MHz
 +
|freq_9=3,500 MHz
 +
|freq_10=3,500 MHz
 +
|freq_11=3,500 MHz
 +
|freq_12=3,500 MHz
 +
|freq_13=3,400 MHz
 +
|freq_14=3,400 MHz
 +
|freq_15=3,400 MHz
 +
|freq_16=3,400 MHz
 +
|freq_17=3,100 MHz
 +
|freq_18=3,100 MHz
 +
|freq_19=3,100 MHz
 +
|freq_20=3,100 MHz
 +
|freq_21=2,900 MHz
 +
|freq_22=2,900 MHz
 +
|freq_23=2,900 MHz
 +
|freq_24=2,900 MHz
 +
|freq_25=2,800 MHz
 +
|freq_26=2,800 MHz
 +
|freq_27=2,800 MHz
 +
|freq_28=2,800 MHz
 +
|freq_avx2_base=1,700 MHz
 +
|freq_avx2_1=3,600 MHz
 +
|freq_avx2_2=3,600 MHz
 +
|freq_avx2_3=3,400 MHz
 +
|freq_avx2_4=3,400 MHz
 +
|freq_avx2_5=3,300 MHz
 +
|freq_avx2_6=3,300 MHz
 +
|freq_avx2_7=3,300 MHz
 +
|freq_avx2_8=3,300 MHz
 +
|freq_avx2_9=3,300 MHz
 +
|freq_avx2_10=3,300 MHz
 +
|freq_avx2_11=3,300 MHz
 +
|freq_avx2_12=3,300 MHz
 +
|freq_avx2_13=2,900 MHz
 +
|freq_avx2_14=2,900 MHz
 +
|freq_avx2_15=2,900 MHz
 +
|freq_avx2_16=2,900 MHz
 +
|freq_avx2_17=2,700 MHz
 +
|freq_avx2_18=2,700 MHz
 +
|freq_avx2_19=2,700 MHz
 +
|freq_avx2_20=2,700 MHz
 +
|freq_avx2_21=2,500 MHz
 +
|freq_avx2_22=2,500 MHz
 +
|freq_avx2_23=2,500 MHz
 +
|freq_avx2_24=2,500 MHz
 +
|freq_avx2_25=2,400 MHz
 +
|freq_avx2_26=2,400 MHz
 +
|freq_avx2_27=2,400 MHz
 +
|freq_avx2_28=2,400 MHz
 +
|freq_avx512_base=1,300 MHz
 +
|freq_avx512_1=3,500 MHz
 +
|freq_avx512_2=3,500 MHz
 +
|freq_avx512_3=3,300 MHz
 +
|freq_avx512_4=3,300 MHz
 +
|freq_avx512_5=3,000 MHz
 +
|freq_avx512_6=3,000 MHz
 +
|freq_avx512_7=3,000 MHz
 +
|freq_avx512_8=3,000 MHz
 +
|freq_avx512_9=2,600 MHz
 +
|freq_avx512_10=2,600 MHz
 +
|freq_avx512_11=2,600 MHz
 +
|freq_avx512_12=2,600 MHz
 +
|freq_avx512_13=2,300 MHz
 +
|freq_avx512_14=2,300 MHz
 +
|freq_avx512_15=2,300 MHz
 +
|freq_avx512_16=2,300 MHz
 +
|freq_avx512_17=2,100 MHz
 +
|freq_avx512_18=2,100 MHz
 +
|freq_avx512_19=2,100 MHz
 +
|freq_avx512_20=2,100 MHz
 +
|freq_avx512_21=2,000 MHz
 +
|freq_avx512_22=2,000 MHz
 +
|freq_avx512_23=2,000 MHz
 +
|freq_avx512_24=2,000 MHz
 +
|freq_avx512_25=1,900 MHz
 +
|freq_avx512_26=1,900 MHz
 +
|freq_avx512_27=1,900 MHz
 +
|freq_avx512_28=1,900 MHz
 +
}}
 +
 +
[[Category:microprocessor models by intel based on skylake extreme core count die]]

Latest revision as of 01:38, 29 December 2019

Edit Values
Xeon Platinum 8176M
skylake sp (basic).png
General Info
DesignerIntel
ManufacturerIntel
Model Number8176M
Part NumberCD8067303133605
S-SpecSR37U
QM7R (QS)
MarketServer
IntroductionApril 25, 2017 (announced)
July 11, 2017 (launched)
Release Price$11722.00
ShopAmazon
General Specs
FamilyXeon Platinum
Series8000
Frequency2,100 MHz
Turbo Frequency3,800 MHz (1 core)
Clock multiplier21
CPUID0x50654
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
PlatformPurley
ChipsetLewisburg
Core NameSkylake SP
Core Family6
Core SteppingH0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores28
Threads56
Max Memory1,536 GiB
Multiprocessing
Max SMP8-Way (Multiprocessor)
InterconnectUPI
Interconnect Links3
Interconnect Rate10.4 GT/s
Electrical
TDP165 W
Tcase0 °C – 89 °C
TDTS0 °C – 97 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Platinum 8176M is a 64-bit 28-core x86 multi-socket highest performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8176M, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.1 GHz with a TDP of 165 W and a turbo boost frequency of up to 3.8 GHz, supports up 1.5 TiB of hexa-channel DDR4-2666 ECC memory.

As indicated by the M suffix, this specific model supports double the memory capacity for up to 1.5 TiB per socket.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.75 MiB
1,792 KiB
1,835,008 B
L1I$896 KiB
917,504 B
0.875 MiB
28x32 KiB8-way set associative 
L1D$896 KiB
917,504 B
0.875 MiB
28x32 KiB8-way set associativewrite-back
L2$28 MiB
28,672 KiB
29,360,128 B
0.0273 GiB
  28x1 MiB16-way set associativewrite-back
L3$38.5 MiB
39,424 KiB
40,370,176 B
0.0376 GiB
  28x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem1,536 GiB
Controllers2
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
Node CtrlrNode Controller Support

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
12345678910111213141516171819202122232425262728
Normal2,100 MHz3,800 MHz3,800 MHz3,600 MHz3,600 MHz3,500 MHz3,500 MHz3,500 MHz3,500 MHz3,500 MHz3,500 MHz3,500 MHz3,500 MHz3,400 MHz3,400 MHz3,400 MHz3,400 MHz3,100 MHz3,100 MHz3,100 MHz3,100 MHz2,900 MHz2,900 MHz2,900 MHz2,900 MHz2,800 MHz2,800 MHz2,800 MHz2,800 MHz
AVX21,700 MHz3,600 MHz3,600 MHz3,400 MHz3,400 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz2,900 MHz2,900 MHz2,900 MHz2,900 MHz2,700 MHz2,700 MHz2,700 MHz2,700 MHz2,500 MHz2,500 MHz2,500 MHz2,500 MHz2,400 MHz2,400 MHz2,400 MHz2,400 MHz
AVX5121,300 MHz3,500 MHz3,500 MHz3,300 MHz3,300 MHz3,000 MHz3,000 MHz3,000 MHz3,000 MHz2,600 MHz2,600 MHz2,600 MHz2,600 MHz2,300 MHz2,300 MHz2,300 MHz2,300 MHz2,100 MHz2,100 MHz2,100 MHz2,100 MHz2,000 MHz2,000 MHz2,000 MHz2,000 MHz1,900 MHz1,900 MHz1,900 MHz1,900 MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_platinum/8176m&oldid=95181"
Facts about "Xeon Platinum 8176M - Intel"
RDF feed
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Xeon Platinum 8176M - Intel#io +
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
chipsetLewisburg +
clock multiplier21 +
core count28 +
core family6 +
core nameSkylake SP +
core steppingH0 +
cpuid0x50654 +
designerIntel +
familyXeon Platinum +
first announcedApril 25, 2017 +
first launchedJuly 11, 2017 +
full page nameintel/xeon platinum/8176m +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size1,792 KiB (1,835,008 B, 1.75 MiB) +
l1d$ description8-way set associative +
l1d$ size896 KiB (917,504 B, 0.875 MiB) +
l1i$ description8-way set associative +
l1i$ size896 KiB (917,504 B, 0.875 MiB) +
l2$ description16-way set associative +
l2$ size28 MiB (28,672 KiB, 29,360,128 B, 0.0273 GiB) +
l3$ description11-way set associative +
l3$ size38.5 MiB (39,424 KiB, 40,370,176 B, 0.0376 GiB) +
ldateJuly 11, 2017 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer +
max case temperature362.15 K (89 °C, 192.2 °F, 651.87 °R) +
max cpu count8 +
max dts temperature97 °C +
max memory1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureSkylake (server) +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature0 °C +
model number8176M +
nameXeon Platinum 8176M +
packageFCLGA-3647 +
part numberCD8067303133605 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 11,722.00 (€ 10,549.80, £ 9,494.82, ¥ 1,211,234.26) +
s-specSR37U +
s-spec (qs)QM7R +
series8000 +
smp interconnectUPI +
smp interconnect links3 +
smp interconnect rate10.4 GT/s +
smp max ways8 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2666 +
tdp165 W (165,000 mW, 0.221 hp, 0.165 kW) +
technologyCMOS +
thread count56 +
turbo frequency (1 core)3,800 MHz (3.8 GHz, 3,800,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +