From WikiChip
					
    Difference between revisions of "intel/xeon e3/e3-1225 v5"    
                	
														| (9 intermediate revisions by 3 users not shown) | |||
| Line 1: | Line 1: | ||
{{intel title|Xeon E3-1225 v5}}  | {{intel title|Xeon E3-1225 v5}}  | ||
| − | {{  | + | {{chip  | 
| − | | name   | + | |name=Xeon E3-1225 v5  | 
| − | |   | + | |image=skylake dt (front).png  | 
| − | + | |designer=Intel  | |
| − | + | |manufacturer=Intel  | |
| − | + | |model number=E3-1225 v5  | |
| − | | designer   | + | |part number=CM8066201922605  | 
| − | | manufacturer   | + | |part number 2=BX80662E31225V5  | 
| − | | model number   | + | |s-spec=SR2CS  | 
| − | | part number   | + | |s-spec 2=SR2LJ  | 
| − | | part number 2   | + | |market=Server  | 
| − | | market   | + | |market 2=Embedded  | 
| − | | market 2   | + | |first announced=October 19, 2015  | 
| − | | first announced   | + | |first launched=October 19, 2015  | 
| − | | first launched   | + | |last order=October 26, 2018  | 
| − | | last order   | + | |last shipment=April 12, 2019  | 
| − | | last shipment   | + | |release price=$224.00  | 
| − | | release price   | + | |family=Xeon E3  | 
| − | + | |series=E3-1200 v5  | |
| − | | family   | + | |locked=Yes  | 
| − | | series   | + | |frequency=3,300 MHz  | 
| − | | locked   | + | |turbo frequency1=3,700 MHz  | 
| − | | frequency   | + | |turbo frequency2=3,600 MHz  | 
| − | | turbo   | + | |turbo frequency3=3,500 MHz  | 
| − | | turbo   | + | |turbo frequency4=3,400 MHz  | 
| − | | turbo   | + | |turbo frequency=Yes  | 
| − | | turbo   | + | |bus type=DMI 3.0  | 
| − | | turbo   | + | |bus links=4  | 
| − | | bus type   | + | |bus rate=8 GT/s  | 
| − | | bus   | + | |clock multiplier=33  | 
| − | | bus rate   | + | |cpuid=506E3  | 
| − | | clock multiplier   | + | |isa=x86-64  | 
| − | + | |isa family=x86  | |
| − | + | |microarch=Skylake  | |
| − | + | |platform=Greenlow  | |
| − | + | |chipset=Sunrise Point  | |
| − | | cpuid   | + | |core name=Skylake DT  | 
| − | + | |core family=6  | |
| − | | isa   | + | |core model=94  | 
| − | | isa   | + | |core stepping=R0  | 
| − | | microarch   | + | |process=14 nm  | 
| − | | platform   | + | |technology=CMOS  | 
| − | | chipset   | + | |die area=122 mm²  | 
| − | | core name   | + | |word size=64 bit  | 
| − | | core family   | + | |core count=4  | 
| − | | core model   | + | |thread count=4  | 
| − | | core stepping   | + | |max cpus=1  | 
| − | | process   | + | |max memory=64 GiB  | 
| − | + | |v core min=0.55 V  | |
| − | | technology   | + | |v core max=1.52 V  | 
| − | | die area   | + | |tdp=80 W  | 
| − | | word size   | + | |tjunc min=0 °C  | 
| − | | core count   | + | |tjunc max=100 °C  | 
| − | | thread count   | + | |tstorage min=-25 °C  | 
| − | | max cpus   | + | |tstorage max=125 °C  | 
| − | | max memory   | + | |package module 1={{packages/intel/lga-1151}}  | 
| − | |||
| − | |||
| − | | v core min   | ||
| − | | v core max   | ||
| − | |||
| − | | tdp   | ||
| − | | tjunc min   | ||
| − | | tjunc max   | ||
| − | |||
| − | |||
| − | | tstorage min   | ||
| − | | tstorage max   | ||
| − | |||
| − | |||
| − | |||
| − | | package module 1   | ||
}}  | }}  | ||
| − | '''Xeon E3-1225 v5''' is an entry-level server and workstation {{arch|64}} [[quad-core]] [[x86]] microprocessor introduced by [[Intel]] in October 2015. This {{intel|Skylake}}-based chip operates at 3.3 GHz with turbo boost of 3.7 GHz. The E3-1225 V5 has a [[TDP]] of   | + | '''Xeon E3-1225 v5''' is an entry-level server and workstation {{arch|64}} [[quad-core]] [[x86]] microprocessor introduced by [[Intel]] in October 2015. This {{intel|Skylake}}-based chip operates at 3.3 GHz with turbo boost of 3.7 GHz. The E3-1225 V5 has a [[TDP]] of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has the {{intel|HD Graphics P530}} [[integrated graphics processor|IGP]].  | 
== Cache ==  | == Cache ==  | ||
| Line 92: | Line 76: | ||
|l3 cache=8 MiB  | |l3 cache=8 MiB  | ||
|l3 break=4x2 MiB  | |l3 break=4x2 MiB  | ||
| − | |||
|l3 policy=write-back  | |l3 policy=write-back  | ||
}}  | }}  | ||
| Line 98: | Line 81: | ||
== Memory controller ==  | == Memory controller ==  | ||
{{memory controller  | {{memory controller  | ||
| − | |type=DDR3L-1600    | + | |type=DDR3L-1600  | 
|type 2=DDR4-2133  | |type 2=DDR4-2133  | ||
|ecc=Yes  | |ecc=Yes  | ||
| Line 104: | Line 87: | ||
|controllers=1  | |controllers=1  | ||
|channels=2  | |channels=2  | ||
| − | |max bandwidth=  | + | |max bandwidth=31.79 GiB/s  | 
| − | |bandwidth schan=  | + | |bandwidth schan=15.89 GiB/s  | 
| − | |bandwidth dchan=  | + | |bandwidth dchan=31.79 GiB/s  | 
}}  | }}  | ||
| Line 145: | Line 128: | ||
| edp ver            = 1.3  | | edp ver            = 1.3  | ||
| max res hdmi       = 4096x2304  | | max res hdmi       = 4096x2304  | ||
| − | | max res hdmi freq  =   | + | | max res hdmi freq  = 24 Hz  | 
| max res dp         = 4096x2304  | | max res dp         = 4096x2304  | ||
| max res dp freq    = 60 Hz  | | max res dp freq    = 60 Hz  | ||
| Line 164: | Line 147: | ||
{{skylake hardware accelerated video table|col=1}}  | {{skylake hardware accelerated video table|col=1}}  | ||
| − | == Features ==    | + | == Features ==  | 
{{x86 features  | {{x86 features  | ||
|real=Yes  | |real=Yes  | ||
| Line 185: | Line 168: | ||
|avx=Yes  | |avx=Yes  | ||
|avx2=Yes  | |avx2=Yes  | ||
| − | + | ||
|abm=Yes  | |abm=Yes  | ||
|tbm=No  | |tbm=No  | ||
| Line 200: | Line 183: | ||
|f16c=Yes  | |f16c=Yes  | ||
|tbt1=No  | |tbt1=No  | ||
| − | |tbt2=  | + | |tbt2=Yes  | 
|tbmt3=No  | |tbmt3=No  | ||
|bpt=No  | |bpt=No  | ||
|eist=Yes  | |eist=Yes  | ||
| − | |sst=  | + | |sst=No  | 
|flex=No  | |flex=No  | ||
|fastmem=No  | |fastmem=No  | ||
| Line 230: | Line 213: | ||
|amdvi=No  | |amdvi=No  | ||
|amdv=No  | |amdv=No  | ||
| + | |amdsme=No  | ||
| + | |amdtsme=No  | ||
| + | |amdsev=No  | ||
|rvi=No  | |rvi=No  | ||
|smt=No  | |smt=No  | ||
Latest revision as of 23:24, 6 April 2018
| Edit Values | ||||||||||||
| Xeon E3-1225 v5 | ||||||||||||
| General Info | ||||||||||||
| Designer | Intel | |||||||||||
| Manufacturer | Intel | |||||||||||
| Model Number | E3-1225 v5 | |||||||||||
| Part Number | CM8066201922605, BX80662E31225V5  | |||||||||||
| S-Spec | SR2CS, SR2LJ | |||||||||||
| Market | Server, Embedded | |||||||||||
| Introduction | October 19, 2015 (announced) October 19, 2015 (launched)  | |||||||||||
| End-of-life | October 26, 2018 (last order) April 12, 2019 (last shipment)  | |||||||||||
| Release Price | $224.00 | |||||||||||
| Shop | Amazon | |||||||||||
| General Specs | ||||||||||||
| Family | Xeon E3 | |||||||||||
| Series | E3-1200 v5 | |||||||||||
| Locked | Yes | |||||||||||
| Frequency | 3,300 MHz | |||||||||||
| Turbo Frequency | Yes | |||||||||||
| Turbo Frequency | 3,700 MHz (1 core), 3,600 MHz (2 cores), 3,500 MHz (3 cores), 3,400 MHz (4 cores)  | |||||||||||
| Bus type | DMI 3.0 | |||||||||||
| Bus rate | 4 × 8 GT/s | |||||||||||
| Clock multiplier | 33 | |||||||||||
| CPUID | 506E3 | |||||||||||
| Microarchitecture | ||||||||||||
| ISA | x86-64 (x86) | |||||||||||
| Microarchitecture | Skylake | |||||||||||
| Platform | Greenlow | |||||||||||
| Chipset | Sunrise Point | |||||||||||
| Core Name | Skylake DT | |||||||||||
| Core Family | 6 | |||||||||||
| Core Model | 94 | |||||||||||
| Core Stepping | R0 | |||||||||||
| Process | 14 nm | |||||||||||
| Technology | CMOS | |||||||||||
| Die | 122 mm² | |||||||||||
| Word Size | 64 bit | |||||||||||
| Cores | 4 | |||||||||||
| Threads | 4 | |||||||||||
| Max Memory | 64 GiB | |||||||||||
| Multiprocessing | ||||||||||||
| Max SMP | 1-Way (Uniprocessor) | |||||||||||
| Electrical | ||||||||||||
| Vcore | 0.55 V-1.52 V | |||||||||||
| TDP | 80 W | |||||||||||
| Tjunction | 0 °C – 100 °C | |||||||||||
| Tstorage | -25 °C – 125 °C | |||||||||||
| Packaging | ||||||||||||
  | ||||||||||||
Xeon E3-1225 v5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 3.3 GHz with turbo boost of 3.7 GHz. The E3-1225 V5 has a TDP of 80 Watts and supports up to 64 GiB of dual-channel DDR4-2133 memory. This MPU has the HD Graphics P530 IGP.
Cache[edit]
- Main article: Skylake § Cache
 
| 
 Cache Organization  
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.  | 
|||||||||||||||||||||||||||||||||||||
  | 
|||||||||||||||||||||||||||||||||||||
Memory controller[edit]
| 
 Integrated Memory Controller 
 | 
||||||||||||||
  | 
||||||||||||||
Expansions[edit]
| 
 Expansion Options 
 | 
||||||||
  | 
||||||||
Graphics[edit]
| 
 Integrated Graphics Information 
 | 
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
  | 
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| [Edit] Skylake (Gen9) Hardware Accelerated Video Capabilities | |||||||
|---|---|---|---|---|---|---|---|
| Codec | Encode | Decode | |||||
| Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
| MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
| MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, SHP, MHP | 5.1 | 2160p (4K) | |
| JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
| HEVC (H.265) | Main | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
| VC-1 | ✘ | Advanced, Main, Simple | 3, High | 3840x3840 | |||
| VP8 | Unified | Unified | - | 0 | Unified | 1080p | |
| VP9 | ✘ | 0 | Unified | 2160p (4K) | |||
Features[edit]
[Edit/Modify Supported Features]
Facts about "Xeon E3-1225 v5  - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.  | Xeon E3-1225 v5 - Intel#package + and Xeon E3-1225 v5 - Intel#io + | 
| base frequency | 3,300 MHz (3.3 GHz, 3,300,000 kHz) + | 
| bus links | 4 + | 
| bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + | 
| bus type | DMI 3.0 + | 
| chipset | Sunrise Point + | 
| clock multiplier | 33 + | 
| core count | 4 + | 
| core family | 6 + | 
| core model | 94 + | 
| core name | Skylake DT + | 
| core stepping | R0 + | 
| core voltage (max) | 1.52 V (15.2 dV, 152 cV, 1,520 mV) + | 
| core voltage (min) | 0.55 V (5.5 dV, 55 cV, 550 mV) + | 
| cpuid | 506E3 + | 
| designer | Intel + | 
| device id | 0x191D + | 
| die area | 122 mm² (0.189 in², 1.22 cm², 122,000,000 µm²) + | 
| family | Xeon E3 + | 
| first announced | October 19, 2015 + | 
| first launched | October 19, 2015 + | 
| full page name | intel/xeon e3/e3-1225 v5 + | 
| has advanced vector extensions | true + | 
| has advanced vector extensions 2 | true + | 
| has ecc memory support | true + | 
| has extended page tables support | true + | 
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology + and OS Guard + | 
| has intel enhanced speedstep technology | true + | 
| has intel secure key technology | true + | 
| has intel supervisor mode execution protection | true + | 
| has intel trusted execution technology | true + | 
| has intel turbo boost technology 2 0 | true + | 
| has intel vpro technology | true + | 
| has intel vt-d technology | true + | 
| has intel vt-x technology | true + | 
| has locked clock multiplier | true + | 
| has second level address translation support | true + | 
| has transactional synchronization extensions | true + | 
| has x86 advanced encryption standard instruction set extension | true + | 
| instance of | microprocessor + | 
| integrated gpu | HD Graphics P530 + | 
| integrated gpu base frequency | 400 MHz (0.4 GHz, 400,000 KHz) + | 
| integrated gpu designer | Intel + | 
| integrated gpu execution units | 24 + | 
| integrated gpu max frequency | 1,150 MHz (1.15 GHz, 1,150,000 KHz) + | 
| integrated gpu max memory | 1,740.8 MiB (1,782,579.2 KiB, 1,825,361,100.8 B, 1.7 GiB) + | 
| isa | x86-64 + | 
| isa family | x86 + | 
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + | 
| l1d$ description | 8-way set associative + | 
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + | 
| l1i$ description | 8-way set associative + | 
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + | 
| l2$ description | 4-way set associative + | 
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + | 
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + | 
| last order | October 26, 2018 + | 
| last shipment | April 12, 2019 + | 
| ldate | October 19, 2015 + | 
| main image | |
| manufacturer | Intel + | 
| market segment | Server + and Embedded + | 
| max cpu count | 1 + | 
| max junction temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + | 
| max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) + | 
| max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + | 
| max memory channels | 2 + | 
| max pcie lanes | 16 + | 
| max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + | 
| microarchitecture | Skylake + | 
| min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + | 
| min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + | 
| model number | E3-1225 v5 + | 
| name | Xeon E3-1225 v5 + | 
| package | FCLGA-1151 + | 
| part number | CM8066201922605 + and BX80662E31225V5 + | 
| platform | Greenlow + | 
| process | 14 nm (0.014 μm, 1.4e-5 mm) + | 
| release price | $ 224.00 (€ 201.60, £ 181.44, ¥ 23,145.92) + | 
| s-spec | SR2CS + and SR2LJ + | 
| series | E3-1200 v5 + | 
| smp max ways | 1 + | 
| socket | LGA-1151 + | 
| supported memory type | DDR3L-1600 + and DDR4-2133 + | 
| tdp | 80 W (80,000 mW, 0.107 hp, 0.08 kW) + | 
| technology | CMOS + | 
| thread count | 4 + | 
| turbo frequency (1 core) | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + | 
| turbo frequency (2 cores) | 3,600 MHz (3.6 GHz, 3,600,000 kHz) + | 
| turbo frequency (3 cores) | 3,500 MHz (3.5 GHz, 3,500,000 kHz) + | 
| turbo frequency (4 cores) | 3,400 MHz (3.4 GHz, 3,400,000 kHz) + | 
| word size | 64 bit (8 octets, 16 nibbles) + | 
| x86/has memory protection extensions | true + | 
| x86/has software guard extensions | true + |