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|extension=FPU | |extension=FPU | ||
|extension 2=NEON | |extension 2=NEON | ||
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|predecessor=Cortex-A73 | |predecessor=Cortex-A73 | ||
|predecessor link=arm_holdings/microarchitectures/cortex-a73 | |predecessor link=arm_holdings/microarchitectures/cortex-a73 | ||
| + | |successor=Cortex-A76 | ||
| + | |successor link=arm_holdings/microarchitectures/cortex-a76 | ||
}} | }} | ||
| + | '''Cortex-A75''' (codename '''Prometheus''') is the successor to the {{armh|Cortex-A73|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A75, which implemented the {{arm|ARMv8.2}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A55}}) in a {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance. | ||
| + | |||
| + | == Compiler su ilepport == | ||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | ! Compiler !! Arch-Specific || Arch-Favorable | ||
| + | |- | ||
| + | | [[Arm Compiler]] || <code>-mcpu=cortex-a75</code> || <code>-mtune=cortex-a75</code> | ||
| + | |- | ||
| + | | [[GCC]] || <code>-mcpu=cortex-a75</code> || <code>-mtune=cortex-a75</code> | ||
| + | |- | ||
| + | | [[LLVM]] || <code>-mcpu=cortex-a75</code> || <code>-mtune=cortex-a75</code> | ||
| + | |} | ||
| + | |||
| + | If the Cortex-A75 is coupled with the {{\\|Cortex-A55}} in a [[big.LITTLE]] system, GCC also supports the following option: | ||
| + | |||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | ! Compiler !! Tune | ||
| + | |- | ||
| + | | [[GCC]] || <code>-mtune=cortex-a75.cortex-a55</code> | ||
| + | |} | ||
| + | |||
| + | == Architecture == | ||
| + | === Key changes from {{\\|Cortex-A73}} === | ||
| + | {{empty section}} | ||
| + | === Block Diagram === | ||
| + | {{empty section}} | ||
| + | === Memory Hierarchy === | ||
| + | {{empty section}} | ||
Latest revision as of 02:26, 6 May 2024
| Edit Values | |
| Cortex-A75 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | May 29, 2017 |
| Process | 16 nm, 14 nm, 10 nm, 7 nm |
| Core Configs | 1, 2 |
| Pipeline | |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 11-13 |
| Decode | 3-way |
| Instructions | |
| ISA | ARMv8.2 |
| Extensions | FPU, NEON |
| Cache | |
| L1I Cache | 8-64 KiB/core 4-way set associative |
| L1D Cache | 8-64 KiB/core 4-way set associative |
| L2 Cache | 64-256-512 KiB/core |
| L3 Cache | 0-4 MiB/Cluster |
| Succession | |
Cortex-A75 (codename Prometheus) is the successor to the Cortex-A73, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A75, which implemented the ARMv8.2 ISA, is the a performant core which is often combined with a number of lower power cores (e.g. Cortex-A55) in a DynamIQ big.LITTLE configuration to achieve better energy/performance.
Contents
Compiler su ilepport[edit]
| Compiler | Arch-Specific | Arch-Favorable |
|---|---|---|
| Arm Compiler | -mcpu=cortex-a75 |
-mtune=cortex-a75
|
| GCC | -mcpu=cortex-a75 |
-mtune=cortex-a75
|
| LLVM | -mcpu=cortex-a75 |
-mtune=cortex-a75
|
If the Cortex-A75 is coupled with the Cortex-A55 in a big.LITTLE system, GCC also supports the following option:
| Compiler | Tune |
|---|---|
| GCC | -mtune=cortex-a75.cortex-a55
|
Architecture[edit]
Key changes from Cortex-A73[edit]
 |
This section is empty; you can help add the missing info by editing this page. |
Block Diagram[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
Facts about "Cortex-A75 - Microarchitectures - ARM"
| codename | Cortex-A75 + |
| core count | 1 + and 2 + |
| designer | ARM Holdings + |
| first launched | May 29, 2017 + |
| full page name | arm holdings/microarchitectures/cortex-a75 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8.2 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-A75 + |
| pipeline stages (max) | 13 + |
| pipeline stages (min) | 11 + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) + |