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Difference between revisions of "intel/xeon gold/5122"
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{{intel title|Xeon Gold 5122}}
 
{{intel title|Xeon Gold 5122}}
−
{{mpu
+
{{chip
−
| future              = Yes
+
|name=Xeon Gold 5122
−
| name               = Xeon Gold 5122
+
|image=skylake sp (basic).png
−
| no image            = Yes
+
|designer=Intel
−
| image              =
+
|manufacturer=Intel
−
| image size          =
+
|model number=5122
−
| caption            =  
+
|part number=BX806735122
−
| designer           = Intel
+
|part number 2=CD8067303330702
−
| manufacturer       = Intel
+
|s-spec=SR3AT
−
| model number       = 5122
+
|s-spec qs=QMRN
−
| part number         = CD8067303330702
+
|market=Server
−
| part number 1      =  
+
|first announced=April 25, 2017
−
| part number 2       =  
+
|first launched=July 11, 2017
−
| s-spec             = SR3AT
+
|release price=$1221.00
−
| s-spec 2            =  
+
|family=Xeon Gold
−
| market             = Server
+
|series=5100
−
| first announced     = April 25, 2017
+
|locked=Yes
−
| first launched     =  
+
|frequency=3,600 MHz
−
| last order          =  
+
|turbo frequency1=3,700 MHz
−
| last shipment      =  
+
|clock multiplier=36
−
| release price      =  
+
|cpuid=0x50654
 +
|isa=x86-64
 +
|isa family=x86
 +
|microarch=Skylake (server)
 +
|platform=Purley
 +
|chipset=Lewisburg
 +
|core name=Skylake SP
 +
|core family=6
 +
|core stepping=H0
 +
|process=14 nm
 +
|technology=CMOS
 +
|word size=64 bit
 +
|core count=4
 +
|thread count=8
 +
|max memory=768 GiB
 +
|max cpus=4
 +
|smp interconnect=UPI
 +
|smp interconnect links=3
 +
|smp interconnect rate=10.4 GT/s
 +
|tdp=105 W
 +
|tcase min=0 °C
 +
|tcase max=71 °C
 +
|dts min=0 °C
 +
|dts max=104 °C
 +
|package name 1=intel,fclga_3647
 +
|successor=Xeon Gold 5222
 +
|successor link=intel/xeon_gold/5222
 +
}}
 +
'''Xeon Gold 5122''' is a {{arch|64}} [[quad-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5122, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] unit as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3.6 GHz with a TDP of 105 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
  
−
| family              = Xeon Gold
+
== Cache ==
−
| series              = 5000
+
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
−
| locked              = Yes
+
The Xeon Gold 5122 features a considerably larger non-default 16.5 MiB of [[L3]], a size that would normally be found on a 12-core part.
−
| frequency          = 3.6 GHz
+
{{cache size
−
| turbo frequency    =  
+
|l1 cache=256 KiB
−
| turbo frequency1    =  
+
|l1i cache=128 KiB
−
| turbo frequency2    =  
+
|l1i break=4x32 KiB
−
| turbo frequency3    =  
+
|l1i desc=8-way set associative
−
| turbo frequency4    =  
+
|l1d cache=128 KiB
−
| turbo frequency5    =  
+
|l1d break=4x32 KiB
−
| turbo frequency6    =  
+
|l1d desc=8-way set associative
−
| turbo frequency7    =  
+
|l1d policy=write-back
−
| turbo frequency8    =  
+
|l2 cache=4 MiB
−
| bus type            = DMI 3.0
+
|l2 break=4x1 MiB
−
| bus speed          =  
+
|l2 desc=16-way set associative
−
| bus rate            = 8 GT/s
+
|l2 policy=write-back
−
| bus links          = 4
+
|l3 cache=16.5 MiB
−
| clock multiplier    = 36
+
|l3 break=12x1.375 MiB
−
| cpuid              =  
+
|l3 desc=11-way set associative
−
| cpuid 2            =  
+
|l3 policy=write-back
 +
}}
  
−
| isa family          = x86-64
+
== Memory controller ==
−
| isa                = x86
+
{{memory controller
−
| microarch          = Skylake
+
|type=DDR4-2666
−
| platform            = Purley
+
|ecc=Yes
−
| chipset            = Lewisburg
+
|max mem=768 GiB
−
| core name          = Skylake SP
+
|controllers=2
−
| core family        =  
+
|channels=6
−
| core model          =  
+
|max bandwidth=119.21 GiB/s
−
| core stepping      = H0
+
|bandwidth schan=19.87 GiB/s
−
| process            = 14 nm
+
|bandwidth dchan=39.74 GiB/s
−
| transistors        =  
+
|bandwidth qchan=79.47 GiB/s
−
| technology          = CMOS
+
|bandwidth hchan=119.21 GiB/s
−
| die area            = <!-- XX mm² -->
+
}}
−
| die width          =  
 
−
| die length          =  
 
−
| word size          = 64 bit
 
−
| core count          =
 
−
| thread count        =
 
−
| max cpus            =
 
−
| max memory          =
 
  
−
| electrical          =  
+
== Expansions ==
−
| power              =  
+
{{expansions
−
| average power      =  
+
| pcie revision     = 3.0
−
| idle power          =  
+
| pcie lanes         = 48
−
| v core              =
+
| pcie config       = x16
−
| v core tolerance    = <!-- OR ... -->
+
| pcie config 2      = x8
−
| v core min          =
+
| pcie config 3      = x4
−
| v core max          =
+
}}
−
| v io                =
 
−
| v io tolerance     =  
 
−
| v io 2              = <!-- OR ... -->
 
−
| v io 3              =
 
−
| sdp                =
 
−
| tdp                =
 
−
| tdp typical         =  
 
−
| ctdp down          =
 
−
| ctdp down frequency =
 
−
| ctdp up            =
 
−
| ctdp up frequency  =
 
−
| temp min            = <!-- use TJ/TC whenever possible instead -->
 
−
| temp max            =
 
−
| tjunc min          = <!-- .. °C -->
 
−
| tjunc max          =
 
−
| tcase min          =
 
−
| tcase max          =
 
−
| tstorage min       =  
 
−
| tstorage max        =  
 
−
| tambient min        =  
 
−
| tambient max        =
 
  
−
| package module 1    =  
+
== Features ==
−
| package module 2   =  
+
{{x86 features
−
<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
+
|real=Yes
−
| packaging          = Yes
+
|protected=Yes
−
| package 0          = FCLGA-3647
+
|smm=Yes
−
| package 0 type      = LGA
+
|fpu=Yes
−
| package 0 pins      = 3647
+
|x8616=Yes
−
| package 0 pitch    =  
+
|x8632=Yes
−
| package 0 width    =  
+
|x8664=Yes
−
| package 0 length    =  
+
|nx=Yes
−
| package 0 height    =  
+
|mmx=Yes
−
| socket 0            = LGA-3647
+
|emmx=Yes
−
| socket 0 type      = LGA
+
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx512vnni=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|avx512units=2
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|bfloat16=No
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=Yes
 +
|intelnodecontroller=No
 +
|intelnode=Yes
 +
|kpt=Yes
 +
|ptt=Yes
 +
|intelrunsure=No
 +
|mbe=Yes
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=No
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|dlboost=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 
}}
 
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=3,600 MHz
 +
|freq_1=3,700 MHz
 +
|freq_2=3,700 MHz
 +
|freq_3=3,700 MHz
 +
|freq_4=3,700 MHz
 +
|freq_avx2_base=3,300 MHz
 +
|freq_avx2_1=3,600 MHz
 +
|freq_avx2_2=3,600 MHz
 +
|freq_avx2_3=3,600 MHz
 +
|freq_avx2_4=3,600 MHz
 +
|freq_avx512_base=2,700 MHz
 +
|freq_avx512_1=3,500 MHz
 +
|freq_avx512_2=3,500 MHz
 +
|freq_avx512_3=3,300 MHz
 +
|freq_avx512_4=3,300 MHz
 +
}}
 +
 +
[[Category:microprocessor models by intel based on skylake extreme core count die]]

Latest revision as of 13:54, 12 January 2020

Edit Values
Xeon Gold 5122
skylake sp (basic).png
General Info
DesignerIntel
ManufacturerIntel
Model Number5122
Part NumberBX806735122,
CD8067303330702
S-SpecSR3AT
QMRN (QS)
MarketServer
IntroductionApril 25, 2017 (announced)
July 11, 2017 (launched)
Release Price$1221.00
ShopAmazon
General Specs
FamilyXeon Gold
Series5100
LockedYes
Frequency3,600 MHz
Turbo Frequency3,700 MHz (1 core)
Clock multiplier36
CPUID0x50654
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
PlatformPurley
ChipsetLewisburg
Core NameSkylake SP
Core Family6
Core SteppingH0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores4
Threads8
Max Memory768 GiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
InterconnectUPI
Interconnect Links3
Interconnect Rate10.4 GT/s
Electrical
TDP105 W
Tcase0 °C – 71 °C
TDTS0 °C – 104 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Gold 5122 is a 64-bit quad-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5122, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA unit as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3.6 GHz with a TDP of 105 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

Cache[edit]

Main article: Skylake § Cache

The Xeon Gold 5122 features a considerably larger non-default 16.5 MiB of L3, a size that would normally be found on a 12-core part.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  4x1 MiB16-way set associativewrite-back
L3$16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
  12x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem768 GiB
Controllers2
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit (2 Units)
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
MBE CtrlMode-Based Execute Control

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
1234
Normal3,600 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz
AVX23,300 MHz3,600 MHz3,600 MHz3,600 MHz3,600 MHz
AVX5122,700 MHz3,500 MHz3,500 MHz3,300 MHz3,300 MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/5122&oldid=95483"
Facts about "Xeon Gold 5122 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 5122 - Intel#io +
base frequency3,600 MHz (3.6 GHz, 3,600,000 kHz) +
chipsetLewisburg +
clock multiplier36 +
core count4 +
core family6 +
core nameSkylake SP +
core steppingH0 +
cpuid0x50654 +
designerIntel +
familyXeon Gold +
first announcedApril 25, 2017 +
first launchedJuly 11, 2017 +
full page nameintel/xeon gold/5122 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description11-way set associative +
l3$ size16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldateJuly 11, 2017 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer +
max case temperature344.15 K (71 °C, 159.8 °F, 619.47 °R) +
max cpu count4 +
max dts temperature104 °C +
max memory786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureSkylake (server) +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature0 °C +
model number5122 +
nameXeon Gold 5122 +
number of avx-512 execution units2 +
packageFCLGA-3647 +
part numberBX806735122 + and CD8067303330702 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 1,221.00 (€ 1,098.90, £ 989.01, ¥ 126,165.93) +
s-specSR3AT +
s-spec (qs)QMRN +
series5100 +
smp interconnectUPI +
smp interconnect links3 +
smp interconnect rate10.4 GT/s +
smp max ways4 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2666 +
tdp105 W (105,000 mW, 0.141 hp, 0.105 kW) +
technologyCMOS +
thread count8 +
turbo frequency (1 core)3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +