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{{intel title|Xeon Gold 6142M}}  | {{intel title|Xeon Gold 6142M}}  | ||
| + | {{chip  | ||
| + | |name=Xeon Gold 6142M  | ||
| + | |image=skylake sp (basic).png  | ||
| + | |designer=Intel  | ||
| + | |manufacturer=Intel  | ||
| + | |model number=6142M  | ||
| + | |part number=CD8067303405700  | ||
| + | |s-spec=SR3B1  | ||
| + | |s-spec qs=QMRW  | ||
| + | |market=Server  | ||
| + | |first announced=April 25, 2017  | ||
| + | |first launched=July 11, 2017  | ||
| + | |release price=$5949.00  | ||
| + | |family=Xeon Gold  | ||
| + | |series=6100  | ||
| + | |locked=Yes  | ||
| + | |frequency=2,600 MHz  | ||
| + | |turbo frequency1=3,700 MHz  | ||
| + | |turbo frequency=Yes  | ||
| + | |clock multiplier=26  | ||
| + | |cpuid=0x50654  | ||
| + | |isa=x86-64  | ||
| + | |isa family=x86  | ||
| + | |microarch=Skylake (server)  | ||
| + | |platform=Purley  | ||
| + | |chipset=Lewisburg  | ||
| + | |core name=Skylake SP  | ||
| + | |core family=6  | ||
| + | |core stepping=H0  | ||
| + | |process=14 nm  | ||
| + | |technology=CMOS  | ||
| + | |word size=64 bit  | ||
| + | |core count=16  | ||
| + | |thread count=32  | ||
| + | |max memory=1,536 GiB  | ||
| + | |max cpus=4  | ||
| + | |smp interconnect=UPI  | ||
| + | |smp interconnect links=3  | ||
| + | |smp interconnect rate=10.4 GT/s  | ||
| + | |tdp=150 W  | ||
| + | |tcase min=0 °C  | ||
| + | |tcase max=85 °C  | ||
| + | |dts min=0 °C  | ||
| + | |dts max=99 °C  | ||
| + | |package name 1=intel,fclga_3647  | ||
| + | }}  | ||
| + | '''Xeon Gold 6142M''' is a {{arch|64}} [[16-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6142M, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.6 GHz with a TDP of 150 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 1.5 TiB of hexa-channel DDR4-2666 ECC memory.  | ||
| + | |||
| + | As indicated by the ''M'' suffix, this specific model supports double the memory capacity for up to 1.5 TiB per socket.  | ||
| + | |||
| + | == Cache ==  | ||
| + | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}  | ||
| + | {{cache size  | ||
| + | |l1 cache=1 MiB  | ||
| + | |l1i cache=512 KiB  | ||
| + | |l1i break=16x32 KiB  | ||
| + | |l1i desc=8-way set associative  | ||
| + | |l1d cache=512 KiB  | ||
| + | |l1d break=16x32 KiB  | ||
| + | |l1d desc=8-way set associative  | ||
| + | |l1d policy=write-back  | ||
| + | |l2 cache=16 MiB  | ||
| + | |l2 break=16x1 MiB  | ||
| + | |l2 desc=16-way set associative  | ||
| + | |l2 policy=write-back  | ||
| + | |l3 cache=22 MiB  | ||
| + | |l3 break=16x1.375 MiB  | ||
| + | |l3 desc=11-way set associative  | ||
| + | |l3 policy=write-back  | ||
| + | }}  | ||
| + | |||
| + | == Memory controller ==  | ||
| + | {{memory controller  | ||
| + | |type=DDR4-2666  | ||
| + | |ecc=Yes  | ||
| + | |max mem=1,536 GiB  | ||
| + | |controllers=2  | ||
| + | |channels=6  | ||
| + | |max bandwidth=119.21 GiB/s  | ||
| + | |bandwidth schan=19.87 GiB/s  | ||
| + | |bandwidth dchan=39.74 GiB/s  | ||
| + | |bandwidth qchan=79.47 GiB/s  | ||
| + | |bandwidth hchan=119.21 GiB/s  | ||
| + | }}  | ||
| + | |||
| + | == Expansions ==  | ||
| + | {{expansions  | ||
| + | | pcie revision      = 3.0  | ||
| + | | pcie lanes         = 48  | ||
| + | | pcie config        = x16  | ||
| + | | pcie config 2      = x8  | ||
| + | | pcie config 3      = x4  | ||
| + | }}  | ||
| + | |||
| + | == Features ==   | ||
| + | {{x86 features  | ||
| + | |real=Yes  | ||
| + | |protected=Yes  | ||
| + | |smm=Yes  | ||
| + | |fpu=Yes  | ||
| + | |x8616=Yes  | ||
| + | |x8632=Yes  | ||
| + | |x8664=Yes  | ||
| + | |nx=Yes  | ||
| + | |mmx=Yes  | ||
| + | |emmx=Yes  | ||
| + | |sse=Yes  | ||
| + | |sse2=Yes  | ||
| + | |sse3=Yes  | ||
| + | |ssse3=Yes  | ||
| + | |sse41=Yes  | ||
| + | |sse42=Yes  | ||
| + | |sse4a=No  | ||
| + | |avx=Yes  | ||
| + | |avx2=Yes  | ||
| + | |avx512f=Yes  | ||
| + | |avx512cd=Yes  | ||
| + | |avx512er=No  | ||
| + | |avx512pf=No  | ||
| + | |avx512bw=Yes  | ||
| + | |avx512dq=Yes  | ||
| + | |avx512vl=Yes  | ||
| + | |avx512ifma=No  | ||
| + | |avx512vbmi=No  | ||
| + | |avx5124fmaps=No  | ||
| + | |avx5124vnniw=No  | ||
| + | |avx512vpopcntdq=No  | ||
| + | |abm=Yes  | ||
| + | |tbm=No  | ||
| + | |bmi1=Yes  | ||
| + | |bmi2=Yes  | ||
| + | |fma3=Yes  | ||
| + | |fma4=No  | ||
| + | |aes=Yes  | ||
| + | |rdrand=Yes  | ||
| + | |sha=No  | ||
| + | |xop=No  | ||
| + | |adx=Yes  | ||
| + | |clmul=Yes  | ||
| + | |f16c=Yes  | ||
| + | |tbt1=No  | ||
| + | |tbt2=Yes  | ||
| + | |tbmt3=No  | ||
| + | |bpt=No  | ||
| + | |eist=Yes  | ||
| + | |sst=Yes  | ||
| + | |flex=No  | ||
| + | |fastmem=No  | ||
| + | |ivmd=Yes  | ||
| + | |intelnodecontroller=Yes  | ||
| + | |intelnode=Yes  | ||
| + | |kpt=Yes  | ||
| + | |ptt=Yes  | ||
| + | |intelrunsure=Yes  | ||
| + | |mbe=Yes  | ||
| + | |isrt=No  | ||
| + | |sba=No  | ||
| + | |mwt=No  | ||
| + | |sipp=No  | ||
| + | |att=No  | ||
| + | |ipt=No  | ||
| + | |tsx=Yes  | ||
| + | |txt=Yes  | ||
| + | |ht=Yes  | ||
| + | |vpro=Yes  | ||
| + | |vtx=Yes  | ||
| + | |vtd=Yes  | ||
| + | |ept=Yes  | ||
| + | |mpx=No  | ||
| + | |sgx=No  | ||
| + | |securekey=No  | ||
| + | |osguard=No  | ||
| + | |3dnow=No  | ||
| + | |e3dnow=No  | ||
| + | |smartmp=No  | ||
| + | |powernow=No  | ||
| + | |amdvi=No  | ||
| + | |amdv=No  | ||
| + | |amdsme=No  | ||
| + | |amdtsme=No  | ||
| + | |amdsev=No  | ||
| + | |rvi=No  | ||
| + | |smt=No  | ||
| + | |sensemi=No  | ||
| + | |xfr=No  | ||
| + | }}  | ||
| + | |||
| + | == Frequencies ==  | ||
| + | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}  | ||
| + | {{frequency table  | ||
| + | |freq_base=2,600 MHz  | ||
| + | |freq_1=3,700 MHz  | ||
| + | |freq_2=3,700 MHz  | ||
| + | |freq_3=3,500 MHz  | ||
| + | |freq_4=3,500 MHz  | ||
| + | |freq_5=3,400 MHz  | ||
| + | |freq_6=3,400 MHz  | ||
| + | |freq_7=3,400 MHz  | ||
| + | |freq_8=3,400 MHz  | ||
| + | |freq_9=3,400 MHz  | ||
| + | |freq_10=3,400 MHz  | ||
| + | |freq_11=3,400 MHz  | ||
| + | |freq_12=3,400 MHz  | ||
| + | |freq_13=3,300 MHz  | ||
| + | |freq_14=3,300 MHz  | ||
| + | |freq_15=3,300 MHz  | ||
| + | |freq_16=3,300 MHz  | ||
| + | |freq_avx2_base=2,200 MHz  | ||
| + | |freq_avx2_1=3,600 MHz  | ||
| + | |freq_avx2_2=3,600 MHz  | ||
| + | |freq_avx2_3=3,400 MHz  | ||
| + | |freq_avx2_4=3,400 MHz  | ||
| + | |freq_avx2_5=3,300 MHz  | ||
| + | |freq_avx2_6=3,300 MHz  | ||
| + | |freq_avx2_7=3,300 MHz  | ||
| + | |freq_avx2_8=3,300 MHz  | ||
| + | |freq_avx2_9=3,200 MHz  | ||
| + | |freq_avx2_10=3,200 MHz  | ||
| + | |freq_avx2_11=3,200 MHz  | ||
| + | |freq_avx2_12=3,200 MHz  | ||
| + | |freq_avx2_13=2,900 MHz  | ||
| + | |freq_avx2_14=2,900 MHz  | ||
| + | |freq_avx2_15=2,900 MHz  | ||
| + | |freq_avx2_16=2,900 MHz  | ||
| + | |freq_avx512_base=1,600 MHz  | ||
| + | |freq_avx512_1=3,500 MHz  | ||
| + | |freq_avx512_2=3,500 MHz  | ||
| + | |freq_avx512_3=3,300 MHz  | ||
| + | |freq_avx512_4=3,300 MHz  | ||
| + | |freq_avx512_5=2,800 MHz  | ||
| + | |freq_avx512_6=2,800 MHz  | ||
| + | |freq_avx512_7=2,800 MHz  | ||
| + | |freq_avx512_8=2,800 MHz  | ||
| + | |freq_avx512_9=2,400 MHz  | ||
| + | |freq_avx512_10=2,400 MHz  | ||
| + | |freq_avx512_11=2,400 MHz  | ||
| + | |freq_avx512_12=2,400 MHz  | ||
| + | |freq_avx512_13=2,200 MHz  | ||
| + | |freq_avx512_14=2,200 MHz  | ||
| + | |freq_avx512_15=2,200 MHz  | ||
| + | |freq_avx512_16=2,200 MHz  | ||
| + | }}  | ||
| + | |||
| + | [[Category:microprocessor models by intel based on skylake extreme core count die]]  | ||
Latest revision as of 00:45, 29 December 2019
| Edit Values | |
| Xeon Gold 6142M | |
| General Info | |
| Designer | Intel | 
| Manufacturer | Intel | 
| Model Number | 6142M | 
| Part Number | CD8067303405700 | 
| S-Spec | SR3B1 QMRW (QS)  | 
| Market | Server | 
| Introduction | April 25, 2017 (announced) July 11, 2017 (launched)  | 
| Release Price | $5949.00 | 
| Shop | Amazon | 
| General Specs | |
| Family | Xeon Gold | 
| Series | 6100 | 
| Locked | Yes | 
| Frequency | 2,600 MHz | 
| Turbo Frequency | Yes | 
| Turbo Frequency | 3,700 MHz (1 core) | 
| Clock multiplier | 26 | 
| CPUID | 0x50654 | 
| Microarchitecture | |
| ISA | x86-64 (x86) | 
| Microarchitecture | Skylake (server) | 
| Platform | Purley | 
| Chipset | Lewisburg | 
| Core Name | Skylake SP | 
| Core Family | 6 | 
| Core Stepping | H0 | 
| Process | 14 nm | 
| Technology | CMOS | 
| Word Size | 64 bit | 
| Cores | 16 | 
| Threads | 32 | 
| Max Memory | 1,536 GiB | 
| Multiprocessing | |
| Max SMP | 4-Way (Multiprocessor) | 
| Interconnect | UPI | 
| Interconnect Links | 3 | 
| Interconnect Rate | 10.4 GT/s | 
| Electrical | |
| TDP | 150 W | 
| Tcase | 0 °C – 85 °C | 
| TDTS | 0 °C – 99 °C | 
| Packaging | |
| Package | FCLGA-3647 (FCLGA) | 
| Dimension | 76.16 mm × 56.6 mm | 
| Pitch | 0.8585 mm × 0.9906 mm | 
| Contacts | 3647 | 
| Socket | Socket P, LGA-3647 | 
Xeon Gold 6142M is a 64-bit 16-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6142M, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.6 GHz with a TDP of 150 W and a turbo boost frequency of up to 3.7 GHz, supports up 1.5 TiB of hexa-channel DDR4-2666 ECC memory.
As indicated by the M suffix, this specific model supports double the memory capacity for up to 1.5 TiB per socket.
Cache[edit]
- Main article: Skylake § Cache
 
| 
 Cache Organization  
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.  | 
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Memory controller[edit]
| 
 Integrated Memory Controller 
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Expansions[edit]
| 
 Expansion Options 
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Features[edit]
[Edit/Modify Supported Features]
| 
 Supported x86 Extensions & Processor Features 
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Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
 
| Mode | Base | Turbo Frequency/Active Cores | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | ||
| Normal | 2,600 MHz | 3,700 MHz | 3,700 MHz | 3,500 MHz | 3,500 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 
| AVX2 | 2,200 MHz | 3,600 MHz | 3,600 MHz | 3,400 MHz | 3,400 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,200 MHz | 3,200 MHz | 3,200 MHz | 3,200 MHz | 2,900 MHz | 2,900 MHz | 2,900 MHz | 2,900 MHz | 
| AVX512 | 1,600 MHz | 3,500 MHz | 3,500 MHz | 3,300 MHz | 3,300 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,200 MHz | 2,200 MHz | 2,200 MHz | 2,200 MHz | 
Facts about "Xeon Gold 6142M  - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.  | Xeon Gold 6142M - Intel#io + | 
| base frequency | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + | 
| chipset | Lewisburg + | 
| clock multiplier | 26 + | 
| core count | 16 + | 
| core family | 6 + | 
| core name | Skylake SP + | 
| core stepping | H0 + | 
| cpuid | 0x50654 + | 
| designer | Intel + | 
| family | Xeon Gold + | 
| first announced | April 25, 2017 + | 
| first launched | July 11, 2017 + | 
| full page name | intel/xeon gold/6142m + | 
| has advanced vector extensions | true + | 
| has advanced vector extensions 2 | true + | 
| has advanced vector extensions 512 | true + | 
| has ecc memory support | true + | 
| has extended page tables support | true + | 
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Transactional Synchronization Extensions +, Turbo Boost Technology 2.0 +, Speed Shift Technology +, Trusted Execution Technology +, Extended Page Tables + and Advanced Vector Extensions 512 + | 
| has intel enhanced speedstep technology | true + | 
| has intel speed shift technology | true + | 
| has intel trusted execution technology | true + | 
| has intel turbo boost technology 2 0 | true + | 
| has intel vpro technology | true + | 
| has intel vt-d technology | true + | 
| has intel vt-x technology | true + | 
| has locked clock multiplier | true + | 
| has second level address translation support | true + | 
| has simultaneous multithreading | true + | 
| has transactional synchronization extensions | true + | 
| has x86 advanced encryption standard instruction set extension | true + | 
| instance of | microprocessor + | 
| isa | x86-64 + | 
| isa family | x86 + | 
| l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + | 
| l1d$ description | 8-way set associative + | 
| l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + | 
| l1i$ description | 8-way set associative + | 
| l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + | 
| l2$ description | 16-way set associative + | 
| l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + | 
| l3$ description | 11-way set associative + | 
| l3$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + | 
| ldate | July 11, 2017 + | 
| main image | |
| manufacturer | Intel + | 
| market segment | Server + | 
| max case temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + | 
| max cpu count | 4 + | 
| max dts temperature | 99 °C + | 
| max memory | 1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) + | 
| max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + | 
| max memory channels | 6 + | 
| max pcie lanes | 48 + | 
| microarchitecture | Skylake (server) + | 
| min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + | 
| min dts temperature | 0 °C + | 
| model number | 6142M + | 
| name | Xeon Gold 6142M + | 
| package | FCLGA-3647 + | 
| part number | CD8067303405700 + | 
| platform | Purley + | 
| process | 14 nm (0.014 μm, 1.4e-5 mm) + | 
| release price | $ 5,949.00 (€ 5,354.10, £ 4,818.69, ¥ 614,710.17) + | 
| s-spec | SR3B1 + | 
| s-spec (qs) | QMRW + | 
| series | 6100 + | 
| smp interconnect | UPI + | 
| smp interconnect links | 3 + | 
| smp interconnect rate | 10.4 GT/s + | 
| smp max ways | 4 + | 
| socket | Socket P + and LGA-3647 + | 
| supported memory type | DDR4-2666 + | 
| tdp | 150 W (150,000 mW, 0.201 hp, 0.15 kW) + | 
| technology | CMOS + | 
| thread count | 32 + | 
| turbo frequency (1 core) | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + | 
| word size | 64 bit (8 octets, 16 nibbles) + |