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Difference between revisions of "intel/xeon gold/6132"
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{{intel title|Xeon Gold 6132}} | {{intel title|Xeon Gold 6132}} | ||
+ | {{chip | ||
+ | |name=Xeon Gold 6132 | ||
+ | |image=skylake sp (basic).png | ||
+ | |designer=Intel | ||
+ | |manufacturer=Intel | ||
+ | |model number=6132 | ||
+ | |part number=CD8067303592500 | ||
+ | |s-spec=SR3J3 | ||
+ | |s-spec qs=QN33 | ||
+ | |market=Server | ||
+ | |first announced=April 25, 2017 | ||
+ | |first launched=July 11, 2017 | ||
+ | |release price=$2111.00 | ||
+ | |family=Xeon Gold | ||
+ | |series=6100 | ||
+ | |locked=Yes | ||
+ | |frequency=2,600 MHz | ||
+ | |turbo frequency1=3,700 MHz | ||
+ | |bus type=DMI 3.0 | ||
+ | |bus links=4 | ||
+ | |bus rate=8 GT/s | ||
+ | |clock multiplier=26 | ||
+ | |cpuid=0x50654 | ||
+ | |isa=x86-64 | ||
+ | |isa family=x86 | ||
+ | |microarch=Skylake (server) | ||
+ | |platform=Purley | ||
+ | |chipset=Lewisburg | ||
+ | |core name=Skylake SP | ||
+ | |core family=6 | ||
+ | |core stepping=H0 | ||
+ | |process=14 nm | ||
+ | |technology=CMOS | ||
+ | |word size=64 bit | ||
+ | |core count=14 | ||
+ | |thread count=28 | ||
+ | |max memory=768 GiB | ||
+ | |max cpus=4 | ||
+ | |smp interconnect=UPI | ||
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
+ | |tdp=140 W | ||
+ | |tcase min=0 °C | ||
+ | |tcase max=86 °C | ||
+ | |dts min=0 °C | ||
+ | |dts max=101 °C | ||
+ | |package name 1=intel,fclga_3647 | ||
+ | }} | ||
+ | '''Xeon Gold 6132''' is a {{arch|64}} [[tetradeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6132, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.6 GHz with a TDP of 140 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=896 KiB | ||
+ | |l1i cache=448 KiB | ||
+ | |l1i break=14x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=448 KiB | ||
+ | |l1d break=14x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=14 MiB | ||
+ | |l2 break=14x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=19.25 MiB | ||
+ | |l3 break=14x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2666 | ||
+ | |ecc=Yes | ||
+ | |max mem=768 GiB | ||
+ | |controllers=2 | ||
+ | |channels=6 | ||
+ | |max bandwidth=119.21 GiB/s | ||
+ | |bandwidth schan=19.87 GiB/s | ||
+ | |bandwidth dchan=39.74 GiB/s | ||
+ | |bandwidth qchan=79.47 GiB/s | ||
+ | |bandwidth hchan=119.21 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 48 | ||
+ | | pcie config = x16 | ||
+ | | pcie config 2 = x8 | ||
+ | | pcie config 3 = x4 | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=Yes | ||
+ | |avx512cd=Yes | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=Yes | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=Yes | ||
+ | |intelnodecontroller=Yes | ||
+ | |intelnode=Yes | ||
+ | |kpt=Yes | ||
+ | |ptt=Yes | ||
+ | |intelrunsure=Yes | ||
+ | |mbe=Yes | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=2,600 MHz | ||
+ | |freq_1=3,700 MHz | ||
+ | |freq_2=3,700 MHz | ||
+ | |freq_3=3,500 MHz | ||
+ | |freq_4=3,500 MHz | ||
+ | |freq_5=3,400 MHz | ||
+ | |freq_6=3,400 MHz | ||
+ | |freq_7=3,400 MHz | ||
+ | |freq_8=3,400 MHz | ||
+ | |freq_9=3,400 MHz | ||
+ | |freq_10=3,400 MHz | ||
+ | |freq_11=3,400 MHz | ||
+ | |freq_12=3,400 MHz | ||
+ | |freq_13=3,300 MHz | ||
+ | |freq_14=3,300 MHz | ||
+ | |freq_avx2_base=2,200 MHz | ||
+ | |freq_avx2_1=3,600 MHz | ||
+ | |freq_avx2_2=3,600 MHz | ||
+ | |freq_avx2_3=3,400 MHz | ||
+ | |freq_avx2_4=3,400 MHz | ||
+ | |freq_avx2_5=3,300 MHz | ||
+ | |freq_avx2_6=3,300 MHz | ||
+ | |freq_avx2_7=3,300 MHz | ||
+ | |freq_avx2_8=3,300 MHz | ||
+ | |freq_avx2_9=3,000 MHz | ||
+ | |freq_avx2_10=3,000 MHz | ||
+ | |freq_avx2_11=3,000 MHz | ||
+ | |freq_avx2_12=3,000 MHz | ||
+ | |freq_avx2_13=2,900 MHz | ||
+ | |freq_avx2_14=2,900 MHz | ||
+ | |freq_avx512_base=1,700 MHz | ||
+ | |freq_avx512_1=3,500 MHz | ||
+ | |freq_avx512_2=3,500 MHz | ||
+ | |freq_avx512_3=3,300 MHz | ||
+ | |freq_avx512_4=3,300 MHz | ||
+ | |freq_avx512_5=2,800 MHz | ||
+ | |freq_avx512_6=2,800 MHz | ||
+ | |freq_avx512_7=2,800 MHz | ||
+ | |freq_avx512_8=2,800 MHz | ||
+ | |freq_avx512_9=2,400 MHz | ||
+ | |freq_avx512_10=2,400 MHz | ||
+ | |freq_avx512_11=2,400 MHz | ||
+ | |freq_avx512_12=2,400 MHz | ||
+ | |freq_avx512_13=2,300 MHz | ||
+ | |freq_avx512_14=2,300 MHz | ||
+ | }} | ||
+ | |||
+ | == Benchmarks == | ||
+ | {{benchmarks main | ||
+ | | | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00371.html|test_timestamp=2017-10-23 22:16:52-0400|chip_count=2|core_count=28|copies_count=56|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)|SPECrate2017_int_base=162|SPECrate2017_int_peak=171}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00373.html|test_timestamp=2017-10-24 01:17:47-0400|chip_count=2|core_count=28|thread_count=28|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)|SPECspeed2017_int_base=8.71|SPECspeed2017_int_peak=8.97}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00377.html|test_timestamp=2017-10-24 06:23:50-0400|chip_count=2|core_count=28|thread_count=28|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)|SPECspeed2017_fp_base=103|SPECspeed2017_fp_peak=104}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00401.html|test_timestamp=2017-10-23 05:14:22-0400|chip_count=2|core_count=28|copies_count=56|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)|SPECrate2017_fp_base=163|SPECrate2017_fp_peak=167}} | ||
+ | }} | ||
+ | |||
+ | [[Category:microprocessor models by intel based on skylake extreme core count die]] |
Latest revision as of 01:20, 29 December 2019
Edit Values | |
Xeon Gold 6132 | |
![]() | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 6132 |
Part Number | CD8067303592500 |
S-Spec | SR3J3 QN33 (QS) |
Market | Server |
Introduction | April 25, 2017 (announced) July 11, 2017 (launched) |
Release Price | $2111.00 |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6100 |
Locked | Yes |
Frequency | 2,600 MHz |
Turbo Frequency | 3,700 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 26 |
CPUID | 0x50654 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | H0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 14 |
Threads | 28 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 140 W |
Tcase | 0 °C – 86 °C |
TDTS | 0 °C – 101 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Xeon Gold 6132 is a 64-bit tetradeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6132, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.6 GHz with a TDP of 140 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Cache[edit]
- Main article: Skylake § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
![]() |
Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
![]() |
Supported x86 Extensions & Processor Features
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Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | ||
Normal | 2,600 MHz | 3,700 MHz | 3,700 MHz | 3,500 MHz | 3,500 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,300 MHz | 3,300 MHz |
AVX2 | 2,200 MHz | 3,600 MHz | 3,600 MHz | 3,400 MHz | 3,400 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,000 MHz | 3,000 MHz | 3,000 MHz | 3,000 MHz | 2,900 MHz | 2,900 MHz |
AVX512 | 1,700 MHz | 3,500 MHz | 3,500 MHz | 3,300 MHz | 3,300 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,800 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,300 MHz | 2,300 MHz |
Benchmarks[edit]
Test: SPEC CPU2017
Tested: 2017-10-23 22:16:52-0400
Chips: 2, Cores: 28, Copies: 56
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)
Tested: 2017-10-23 22:16:52-0400
Chips: 2, Cores: 28, Copies: 56
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)
SPECrate2017_int_base: 162
SPECrate2017_int_peak: 171
Test: SPEC CPU2017
Tested: 2017-10-24 01:17:47-0400
Chips: 2, Cores: 28, Threads: 28
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)
Tested: 2017-10-24 01:17:47-0400
Chips: 2, Cores: 28, Threads: 28
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)
SPECspeed2017_int_base: 8.71
SPECspeed2017_int_peak: 8.97
Test: SPEC CPU2017
Tested: 2017-10-24 06:23:50-0400
Chips: 2, Cores: 28, Threads: 28
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)
Tested: 2017-10-24 06:23:50-0400
Chips: 2, Cores: 28, Threads: 28
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)
SPECspeed2017_fp_base: 103
SPECspeed2017_fp_peak: 104
Test: SPEC CPU2017
Tested: 2017-10-23 05:14:22-0400
Chips: 2, Cores: 28, Copies: 56
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)
Tested: 2017-10-23 05:14:22-0400
Chips: 2, Cores: 28, Copies: 56
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: Cisco UCS B200 M5 (Intel Xeon Gold 6132, 2.60GHz)
SPECrate2017_fp_base: 163
SPECrate2017_fp_peak: 167
Facts about "Xeon Gold 6132 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6132 - Intel#io +, Xeon Gold 6132 - Intel +, Xeon Gold 6132 - Intel +, Xeon Gold 6132 - Intel + and Xeon Gold 6132 - Intel + |
base frequency | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 26 + |
core count | 14 + |
core family | 6 + |
core name | Skylake SP + |
core stepping | H0 + |
cpuid | 0x50654 + |
designer | Intel + |
family | Xeon Gold + |
first announced | April 25, 2017 + |
first launched | July 11, 2017 + |
full page name | intel/xeon gold/6132 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 896 KiB (917,504 B, 0.875 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 14 MiB (14,336 KiB, 14,680,064 B, 0.0137 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 19.25 MiB (19,712 KiB, 20,185,088 B, 0.0188 GiB) + |
ldate | July 11, 2017 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 359.15 K (86 °C, 186.8 °F, 646.47 °R) + |
max cpu count | 4 + |
max dts temperature | 101 °C + |
max memory | 786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
microarchitecture | Skylake (server) + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min dts temperature | 0 °C + |
model number | 6132 + |
name | Xeon Gold 6132 + |
package | FCLGA-3647 + |
part number | CD8067303592500 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 2,111.00 (€ 1,899.90, £ 1,709.91, ¥ 218,129.63) + |
s-spec | SR3J3 + |
s-spec (qs) | QN33 + |
series | 6100 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2666 + |
tdp | 140 W (140,000 mW, 0.188 hp, 0.14 kW) + |
technology | CMOS + |
thread count | 28 + |
turbo frequency (1 core) | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |