From WikiChip
Difference between revisions of "intel/xeon gold/6126"
(Created page with "{{intel title|Xeon Gold 6126}}") |
|||
(34 intermediate revisions by 5 users not shown) | |||
Line 1: | Line 1: | ||
{{intel title|Xeon Gold 6126}} | {{intel title|Xeon Gold 6126}} | ||
+ | {{chip | ||
+ | |name=Xeon Gold 6126 | ||
+ | |image=skylake sp (basic).png | ||
+ | |designer=Intel | ||
+ | |manufacturer=Intel | ||
+ | |model number=6126 | ||
+ | |part number=CD8067303405900 | ||
+ | |s-spec=SR3B3 | ||
+ | |s-spec qs=QMRY | ||
+ | |market=Server | ||
+ | |first announced=April 25, 2017 | ||
+ | |first launched=July 11, 2017 | ||
+ | |release price=$1776.00 | ||
+ | |family=Xeon Gold | ||
+ | |series=6100 | ||
+ | |locked=Yes | ||
+ | |frequency=2,600 MHz | ||
+ | |turbo frequency1=3,700 MHz | ||
+ | |bus type=DMI 3.0 | ||
+ | |bus links=4 | ||
+ | |bus rate=8 GT/s | ||
+ | |clock multiplier=26 | ||
+ | |cpuid=0x50654 | ||
+ | |isa=x86-64 | ||
+ | |isa family=x86 | ||
+ | |microarch=Skylake (server) | ||
+ | |platform=Purley | ||
+ | |chipset=Lewisburg | ||
+ | |core name=Skylake SP | ||
+ | |core family=6 | ||
+ | |core stepping=H0 | ||
+ | |process=14 nm | ||
+ | |technology=CMOS | ||
+ | |word size=64 bit | ||
+ | |core count=12 | ||
+ | |thread count=24 | ||
+ | |max memory=768 GiB | ||
+ | |max cpus=4 | ||
+ | |smp interconnect=UPI | ||
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
+ | |tdp=125 W | ||
+ | |tcase min=0 °C | ||
+ | |tcase max=86 °C | ||
+ | |dts min=0 °C | ||
+ | |dts max=100 °C | ||
+ | |package name 1=intel,fclga_3647 | ||
+ | |successor=Xeon Gold 6226 | ||
+ | |successor link=intel/xeon_gold/6226 | ||
+ | }} | ||
+ | '''Xeon Gold 6126''' is a {{arch|64}} [[dodeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6126, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.6 GHz with a TDP of 125 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} | ||
+ | The Xeon Gold 6126 features a considerably larger non-default 19.25 MiB of [[L3]], a size that would normally be found on a 14-core part. | ||
+ | {{cache size | ||
+ | |l1 cache=768 KiB | ||
+ | |l1i cache=384 KiB | ||
+ | |l1i break=12x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=384 KiB | ||
+ | |l1d break=12x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=12 MiB | ||
+ | |l2 break=12x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=19.25 MiB | ||
+ | |l3 break=14x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2666 | ||
+ | |ecc=Yes | ||
+ | |max mem=768 GiB | ||
+ | |controllers=2 | ||
+ | |channels=6 | ||
+ | |max bandwidth=119.21 GiB/s | ||
+ | |bandwidth schan=19.87 GiB/s | ||
+ | |bandwidth dchan=39.74 GiB/s | ||
+ | |bandwidth qchan=79.47 GiB/s | ||
+ | |bandwidth hchan=119.21 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 48 | ||
+ | | pcie config = x16 | ||
+ | | pcie config 2 = x8 | ||
+ | | pcie config 3 = x4 | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=Yes | ||
+ | |avx512cd=Yes | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=Yes | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=Yes | ||
+ | |intelnodecontroller=Yes | ||
+ | |intelnode=Yes | ||
+ | |kpt=Yes | ||
+ | |ptt=Yes | ||
+ | |intelrunsure=Yes | ||
+ | |mbe=Yes | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=2,600 MHz | ||
+ | |freq_1=3,700 MHz | ||
+ | |freq_2=3,700 MHz | ||
+ | |freq_3=3,500 MHz | ||
+ | |freq_4=3,500 MHz | ||
+ | |freq_5=3,400 MHz | ||
+ | |freq_6=3,400 MHz | ||
+ | |freq_7=3,400 MHz | ||
+ | |freq_8=3,400 MHz | ||
+ | |freq_9=3,300 MHz | ||
+ | |freq_10=3,300 MHz | ||
+ | |freq_11=3,300 MHz | ||
+ | |freq_12=3,300 MHz | ||
+ | |freq_avx2_base=2,200 MHz | ||
+ | |freq_avx2_1=3,600 MHz | ||
+ | |freq_avx2_2=3,600 MHz | ||
+ | |freq_avx2_3=3,400 MHz | ||
+ | |freq_avx2_4=3,400 MHz | ||
+ | |freq_avx2_5=3,300 MHz | ||
+ | |freq_avx2_6=3,300 MHz | ||
+ | |freq_avx2_7=3,300 MHz | ||
+ | |freq_avx2_8=3,300 MHz | ||
+ | |freq_avx2_9=2,900 MHz | ||
+ | |freq_avx2_10=2,900 MHz | ||
+ | |freq_avx2_11=2,900 MHz | ||
+ | |freq_avx2_12=2,900 MHz | ||
+ | |freq_avx512_base=1,700 MHz | ||
+ | |freq_avx512_1=3,500 MHz | ||
+ | |freq_avx512_2=3,500 MHz | ||
+ | |freq_avx512_3=3,300 MHz | ||
+ | |freq_avx512_4=3,300 MHz | ||
+ | |freq_avx512_5=2,600 MHz | ||
+ | |freq_avx512_6=2,600 MHz | ||
+ | |freq_avx512_7=2,600 MHz | ||
+ | |freq_avx512_8=2,600 MHz | ||
+ | |freq_avx512_9=2,300 MHz | ||
+ | |freq_avx512_10=2,300 MHz | ||
+ | |freq_avx512_11=2,300 MHz | ||
+ | |freq_avx512_12=2,300 MHz | ||
+ | }} | ||
+ | |||
+ | == Benchmarks == | ||
+ | {{benchmarks main | ||
+ | | | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00127.html|test_timestamp=2017-10-15 14:10:09-0400|chip_count=2|core_count=24|thread_count=24|vendor=HPE|system=ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Gold 6126)|SPECspeed2017_fp_base=94.7|SPECspeed2017_fp_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00150.html|test_timestamp=2017-10-15 15:27:17-0400|chip_count=2|core_count=24|thread_count=24|vendor=HPE|system=ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Gold 6126)|SPECspeed2017_int_base=8.63|SPECspeed2017_int_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00200.html|test_timestamp=2017-10-09 05:16:12-0400|chip_count=2|core_count=24|copies_count=48|vendor=HPE|system=ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Gold 6126)|SPECrate2017_int_base=141|SPECrate2017_int_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00202.html|test_timestamp=2017-10-09 09:53:49-0400|chip_count=2|core_count=24|copies_count=48|vendor=HPE|system=ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Gold 6126)|SPECrate2017_fp_base=149|SPECrate2017_fp_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00214.html|test_timestamp=2017-10-06 15:05:04-0400|chip_count=2|core_count=24|thread_count=24|vendor=HPE|system=ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Gold 6126)|SPECspeed2017_fp_base=94.2|SPECspeed2017_fp_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00451.html|test_timestamp=2017-10-23 03:30:18-0400|chip_count=2|core_count=24|copies_count=48|vendor=HPE|system=ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Gold 6126)|SPECrate2017_int_base=136|SPECrate2017_int_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00461.html|test_timestamp=2017-10-06 11:59:24-0400|chip_count=2|core_count=24|thread_count=24|vendor=HPE|system=ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Gold 6126)|SPECspeed2017_int_base=8.63|SPECspeed2017_int_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00465.html|test_timestamp=2017-10-23 08:07:59-0400|chip_count=2|core_count=24|copies_count=48|vendor=HPE|system=ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Gold 6126)|SPECrate2017_fp_base=144|SPECrate2017_fp_peak=}} | ||
+ | }} | ||
+ | |||
+ | [[Category:microprocessor models by intel based on skylake extreme core count die]] |
Latest revision as of 00:20, 29 December 2019
Edit Values | |
Xeon Gold 6126 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 6126 |
Part Number | CD8067303405900 |
S-Spec | SR3B3 QMRY (QS) |
Market | Server |
Introduction | April 25, 2017 (announced) July 11, 2017 (launched) |
Release Price | $1776.00 |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6100 |
Locked | Yes |
Frequency | 2,600 MHz |
Turbo Frequency | 3,700 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 26 |
CPUID | 0x50654 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | H0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 12 |
Threads | 24 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 125 W |
Tcase | 0 °C – 86 °C |
TDTS | 0 °C – 100 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Xeon Gold 6126 is a 64-bit dodeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6126, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.6 GHz with a TDP of 125 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Cache[edit]
- Main article: Skylake § Cache
The Xeon Gold 6126 features a considerably larger non-default 19.25 MiB of L3, a size that would normally be found on a 14-core part.
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller[edit]
Integrated Memory Controller
|
||||||||||||||
|
Expansions[edit]
Expansion Options
|
||||||||
|
Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | ||
Normal | 2,600 MHz | 3,700 MHz | 3,700 MHz | 3,500 MHz | 3,500 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz |
AVX2 | 2,200 MHz | 3,600 MHz | 3,600 MHz | 3,400 MHz | 3,400 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 2,900 MHz | 2,900 MHz | 2,900 MHz | 2,900 MHz |
AVX512 | 1,700 MHz | 3,500 MHz | 3,500 MHz | 3,300 MHz | 3,300 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,300 MHz | 2,300 MHz | 2,300 MHz | 2,300 MHz |
Benchmarks[edit]
Test: SPEC CPU2017
Tested: 2017-10-15 14:10:09-0400
Chips: 2, Cores: 24, Threads: 24
Tested: 2017-10-15 14:10:09-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: HPE
System: ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Gold 6126)
System: ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Gold 6126)
SPECspeed2017_fp_base: 94.7
Test: SPEC CPU2017
Tested: 2017-10-15 15:27:17-0400
Chips: 2, Cores: 24, Threads: 24
Tested: 2017-10-15 15:27:17-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: HPE
System: ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Gold 6126)
System: ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Gold 6126)
SPECspeed2017_int_base: 8.63
Test: SPEC CPU2017
Tested: 2017-10-09 05:16:12-0400
Chips: 2, Cores: 24, Copies: 48
Tested: 2017-10-09 05:16:12-0400
Chips: 2, Cores: 24, Copies: 48
Vendor: HPE
System: ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Gold 6126)
System: ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Gold 6126)
SPECrate2017_int_base: 141
Test: SPEC CPU2017
Tested: 2017-10-09 09:53:49-0400
Chips: 2, Cores: 24, Copies: 48
Tested: 2017-10-09 09:53:49-0400
Chips: 2, Cores: 24, Copies: 48
Vendor: HPE
System: ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Gold 6126)
System: ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Gold 6126)
SPECrate2017_fp_base: 149
Test: SPEC CPU2017
Tested: 2017-10-06 15:05:04-0400
Chips: 2, Cores: 24, Threads: 24
Tested: 2017-10-06 15:05:04-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: HPE
System: ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Gold 6126)
System: ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Gold 6126)
SPECspeed2017_fp_base: 94.2
Test: SPEC CPU2017
Tested: 2017-10-23 03:30:18-0400
Chips: 2, Cores: 24, Copies: 48
Tested: 2017-10-23 03:30:18-0400
Chips: 2, Cores: 24, Copies: 48
Vendor: HPE
System: ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Gold 6126)
System: ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Gold 6126)
SPECrate2017_int_base: 136
Test: SPEC CPU2017
Tested: 2017-10-06 11:59:24-0400
Chips: 2, Cores: 24, Threads: 24
Tested: 2017-10-06 11:59:24-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: HPE
System: ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Gold 6126)
System: ProLiant DL380 Gen10 (2.60 GHz, Intel Xeon Gold 6126)
SPECspeed2017_int_base: 8.63
Test: SPEC CPU2017
Tested: 2017-10-23 08:07:59-0400
Chips: 2, Cores: 24, Copies: 48
Tested: 2017-10-23 08:07:59-0400
Chips: 2, Cores: 24, Copies: 48
Vendor: HPE
System: ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Gold 6126)
System: ProLiant DL360 Gen10 (2.60 GHz, Intel Xeon Gold 6126)
SPECrate2017_fp_base: 144
Facts about "Xeon Gold 6126 - Intel"