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{{intel title|Atom Z625}} | {{intel title|Atom Z625}} | ||
− | {{ | + | {{chip |
| name = Atom Z625 | | name = Atom Z625 | ||
− | + | | image = lincroft chips.png | |
− | | image = | + | | image size = 250px |
− | | image size = | ||
| caption = | | caption = | ||
| designer = Intel | | designer = Intel | ||
Line 10: | Line 9: | ||
| model number = Z625 | | model number = Z625 | ||
| part number = AY80609003987AB | | part number = AY80609003987AB | ||
− | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| s-spec = SLBZD | | s-spec = SLBZD | ||
| s-spec 2 = | | s-spec 2 = | ||
Line 59: | Line 58: | ||
| max memory = 2 GiB | | max memory = 2 GiB | ||
− | + | ||
| power = | | power = | ||
| average power = | | average power = | ||
Line 89: | Line 88: | ||
| package module 1 = {{packages/intel/fcbga-518}} | | package module 1 = {{packages/intel/fcbga-518}} | ||
}} | }} | ||
− | '''Atom Z625''' is an ultra-low power {{arch|32}} [[x86]] system on a chip designed by [[Intel]] and introduced in early [[2010]]. The Z625, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Lincroft|l=core}} core), is fabricated on a [[45 nm process]]. This SoC incorporates a single core operating at 1.5 GHz with a low frequency mode of 600 MHz and a burst frequency of 1.9 GHz. The chip has a TDP of 2.2 W and supporting up to a 2 GiB of single-channel DDR2-800 memory. Additionally, the Z625 incorporates | + | '''Atom Z625''' is an ultra-low power {{arch|32}} [[x86]] system on a chip designed by [[Intel]] and introduced in early [[2010]]. The Z625, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Lincroft|l=core}} core), is fabricated on a [[45 nm process]]. This SoC incorporates a single core operating at 1.5 GHz with a low frequency mode of 600 MHz and a burst frequency of 1.9 GHz. The chip has a TDP of 2.2 W and supporting up to a 2 GiB of single-channel DDR2-800 memory. Additionally, the Z625 incorporates a {{imgtec|PowerVR SGX 535|GMA 600}} [[IGP]] operating at 400 MHz. |
+ | |||
+ | This chip communicates with the [[southbridge]] chipset (PCH MP30) over two buses: cDMI and cDVO. Both buses go from the SoC to the chipset. cDMI, which is used as the data interface link, operates at 100 MHz using a quad-pumped rate (i.e. 400 MT/s). That bus is composed of an 8-bit transmit and 8-bit receive. The cDVO, which is used as a unidirectional display data link is a quad-pumped 6-bit bus operating 200 MHz for a 800 MT/s effective rate. This model uses a [[GTL|AGTL+]] signaling bus for this. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/bonnell#Memory_Hierarchy|l1=Bonnell § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=56 KiB | ||
+ | |l1i cache=32 KiB | ||
+ | |l1i break=1x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=24 KiB | ||
+ | |l1d break=1x24 KiB | ||
+ | |l1d desc=6-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=512 KiB | ||
+ | |l2 break=1x512 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR-400 | ||
+ | |type 2=DDR2-800 | ||
+ | |ecc=No | ||
+ | |max mem=2 GiB | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=32 bit | ||
+ | |max bandwidth=2.98 GiB/s | ||
+ | |bandwidth schan=2.98 GiB/s | ||
+ | |pae=32 bit | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | usb revision = 2.0 | ||
+ | | usb ports = 4 | ||
+ | | uart = Yes | ||
+ | | gp io = Yes | ||
+ | }} | ||
+ | |||
+ | == Graphics == | ||
+ | This chip incroporates the "GMA 600" integrated graphics which is actually a re-branded licensed [[Imagination Technologies|Imagination]] {{imgtec|PowerVR SGX 535}} [[IGP]]. | ||
+ | {{integrated graphics | ||
+ | | gpu = PowerVR SGX535 | ||
+ | | device id = | ||
+ | | designer = Imagination Technologies | ||
+ | | execution units = | ||
+ | | max displays = 1 | ||
+ | | max memory = 256 MiB | ||
+ | | frequency = 400 MHz | ||
+ | |||
+ | | output dsi = Yes | ||
+ | | output lvds = Yes | ||
+ | |||
+ | | max res dsi = 1024x600 | ||
+ | | max res lvds = 1366x768 | ||
+ | |||
+ | | direct3d ver = 9.0c | ||
+ | | opengl ver = 2.1 | ||
+ | | openvg ver = 1.1 | ||
+ | | opengl es ver = 1.1 | ||
+ | | opengl es ver 2 = 2.0 | ||
+ | |||
+ | | features = Yes | ||
+ | | intel clear video = Yes | ||
+ | }} | ||
+ | |||
+ | * Supports hardware-accelerated HD video decode (MPEG4 part 2, H.264, WMV, and VC1) | ||
+ | * Supports hardware-accelerated HD video encode (MPEG4 part 2 and H.264) | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=No | ||
+ | |sse42=No | ||
+ | |sse4a=No | ||
+ | |avx=No | ||
+ | |avx2=No | ||
+ | |||
+ | |abm=No | ||
+ | |tbm=No | ||
+ | |bmi1=No | ||
+ | |bmi2=No | ||
+ | |fma3=No | ||
+ | |fma4=No | ||
+ | |aes=No | ||
+ | |rdrand=No | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=No | ||
+ | |clmul=No | ||
+ | |f16c=No | ||
+ | |tbt1=No | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |bpt=Yes | ||
+ | |eist=Yes | ||
+ | |sst=No | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=No | ||
+ | |txt=No | ||
+ | |ht=Yes | ||
+ | |vpro=No | ||
+ | |vtx=No | ||
+ | |vtd=No | ||
+ | |ept=No | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | }} | ||
+ | |||
+ | == Die Shot == | ||
+ | {{see also|intel/microarchitectures/bonnell#Lincroft|l1=Bonnell § Lincroft Die}} | ||
+ | * [[45 nm process]] | ||
+ | * 140,000,000 | ||
+ | * Die size 7.34 mm × 8.89 mm | ||
+ | * Size area 65.2526 mm² | ||
+ | [[File:lincroft die shot.png|500px]] | ||
+ | |||
+ | [[File:lincroft die shot (annotated).png|500px]] | ||
+ | |||
+ | |||
+ | [[File:lincroft die shot 2.png|500px]] | ||
+ | |||
+ | [[File:lincroft die shot 2 (annotated).png|500px]] | ||
+ | |||
+ | == Documents == | ||
+ | === Datasheet === | ||
+ | * [[:File:atom-z6xx-datasheet.pdf|Atom Z6xx Datasheet]], May 2011 | ||
+ | * [[:File:atom-z6xx-specification-update.pdf|Atom Z6xx Specs Update]], May 2011 |
Latest revision as of 15:15, 13 December 2017
Edit Values | |||||||||
Atom Z625 | |||||||||
General Info | |||||||||
Designer | Intel | ||||||||
Manufacturer | Intel | ||||||||
Model Number | Z625 | ||||||||
Part Number | AY80609003987AB | ||||||||
S-Spec | SLBZD | ||||||||
Market | Mobile | ||||||||
Introduction | May 4, 2010 (announced) May 4, 2010 (launched) | ||||||||
Shop | Amazon | ||||||||
General Specs | |||||||||
Family | Atom | ||||||||
Series | Z600 | ||||||||
Locked | Yes | ||||||||
Frequency | 1,500 MHz | ||||||||
Turbo Frequency | Yes | ||||||||
Turbo Frequency | 1,900 MHz (1 core) | ||||||||
Bus type | cDMI | ||||||||
Bus speed | 100 MHz | ||||||||
Bus rate | 400 MT/s | ||||||||
Clock multiplier | 15 | ||||||||
CPUID | 20661 | ||||||||
Microarchitecture | |||||||||
ISA | x86-32 (x86) | ||||||||
Microarchitecture | Bonnell | ||||||||
Platform | Moorestown | ||||||||
Chipset | Langwell | ||||||||
Core Name | Lincroft | ||||||||
Core Family | 6 | ||||||||
Core Model | 38 | ||||||||
Core Stepping | 1 | ||||||||
Process | 45 nm | ||||||||
Transistors | 140,000,000 | ||||||||
Technology | CMOS | ||||||||
Die | 65.2526 mm² 8.89 mm × 7.34 mm | ||||||||
Word Size | 32 bit | ||||||||
Cores | 1 | ||||||||
Threads | 2 | ||||||||
Max Memory | 2 GiB | ||||||||
Multiprocessing | |||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||
Electrical | |||||||||
Vcore | 0.75 V-1.2 V | ||||||||
TDP | 2.2 W | ||||||||
Tjunction | 0 °C – 90 °C | ||||||||
Tstorage | -55 °C – 125 °C | ||||||||
Packaging | |||||||||
|
Atom Z625 is an ultra-low power 32-bit x86 system on a chip designed by Intel and introduced in early 2010. The Z625, which is based on the Bonnell microarchitecture (Lincroft core), is fabricated on a 45 nm process. This SoC incorporates a single core operating at 1.5 GHz with a low frequency mode of 600 MHz and a burst frequency of 1.9 GHz. The chip has a TDP of 2.2 W and supporting up to a 2 GiB of single-channel DDR2-800 memory. Additionally, the Z625 incorporates a GMA 600 IGP operating at 400 MHz.
This chip communicates with the southbridge chipset (PCH MP30) over two buses: cDMI and cDVO. Both buses go from the SoC to the chipset. cDMI, which is used as the data interface link, operates at 100 MHz using a quad-pumped rate (i.e. 400 MT/s). That bus is composed of an 8-bit transmit and 8-bit receive. The cDVO, which is used as a unidirectional display data link is a quad-pumped 6-bit bus operating 200 MHz for a 800 MT/s effective rate. This model uses a AGTL+ signaling bus for this.
Contents
Cache[edit]
- Main article: Bonnell § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Graphics[edit]
This chip incroporates the "GMA 600" integrated graphics which is actually a re-branded licensed Imagination PowerVR SGX 535 IGP.
Integrated Graphics Information
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- Supports hardware-accelerated HD video decode (MPEG4 part 2, H.264, WMV, and VC1)
- Supports hardware-accelerated HD video encode (MPEG4 part 2 and H.264)
Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Die Shot[edit]
- See also: Bonnell § Lincroft Die
- 45 nm process
- 140,000,000
- Die size 7.34 mm × 8.89 mm
- Size area 65.2526 mm²
Documents[edit]
Datasheet[edit]
- Atom Z6xx Datasheet, May 2011
- Atom Z6xx Specs Update, May 2011
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Atom Z625 - Intel#package + |
base frequency | 1,500 MHz (1.5 GHz, 1,500,000 kHz) + |
bus rate | 400 MT/s (0.4 GT/s, 400,000 kT/s) + |
bus speed | 100 MHz (0.1 GHz, 100,000 kHz) + |
bus type | cDMI + |
chipset | Langwell + |
clock multiplier | 15 + |
core count | 1 + |
core family | 6 + |
core model | 38 + |
core name | Lincroft + |
core stepping | 1 + |
core voltage (max) | 1.2 V (12 dV, 120 cV, 1,200 mV) + |
core voltage (min) | 0.75 V (7.5 dV, 75 cV, 750 mV) + |
cpuid | 20661 + |
designer | Intel + |
die area | 65.253 mm² (0.101 in², 0.653 cm², 65,252,600 µm²) + |
die length | 8.89 mm (0.889 cm, 0.35 in, 8,890 µm) + |
die width | 7.34 mm (0.734 cm, 0.289 in, 7,340 µm) + |
family | Atom + |
first announced | May 4, 2010 + |
first launched | May 4, 2010 + |
full page name | intel/atom/z625 + |
has ecc memory support | false + |
has feature | Hyper-Threading Technology +, Burst Performance Technology + and Enhanced SpeedStep Technology + |
has intel burst performance technology | true + |
has intel enhanced speedstep technology | true + |
has locked clock multiplier | true + |
has simultaneous multithreading | true + |
instance of | microprocessor + |
integrated gpu | PowerVR SGX535 + |
integrated gpu base frequency | 400 MHz (0.4 GHz, 400,000 KHz) + |
integrated gpu designer | Imagination Technologies + |
integrated gpu max memory | 256 MiB (262,144 KiB, 268,435,456 B, 0.25 GiB) + |
isa | x86-32 + |
isa family | x86 + |
l1$ size | 56 KiB (57,344 B, 0.0547 MiB) + |
l1d$ description | 6-way set associative + |
l1d$ size | 24 KiB (24,576 B, 0.0234 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
ldate | May 4, 2010 + |
main image | + |
manufacturer | Intel + |
market segment | Mobile + |
max cpu count | 1 + |
max junction temperature | 363.15 K (90 °C, 194 °F, 653.67 °R) + |
max memory | 2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) + |
max memory bandwidth | 2.98 GiB/s (3,051.52 MiB/s, 3.2 GB/s, 3,199.751 MB/s, 0.00291 TiB/s, 0.0032 TB/s) + |
max memory channels | 1 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Bonnell + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 218.15 K (-55 °C, -67 °F, 392.67 °R) + |
model number | Z625 + |
name | Atom Z625 + |
package | FCBGA-518 + |
part number | AY80609003987AB + |
platform | Moorestown + |
process | 45 nm (0.045 μm, 4.5e-5 mm) + |
s-spec | SLBZD + |
series | Z600 + |
smp max ways | 1 + |
socket | BGA-518 + |
supported memory type | DDR-400 + and DDR2-800 + |
tdp | 2.2 W (2,200 mW, 0.00295 hp, 0.0022 kW) + |
technology | CMOS + |
thread count | 2 + |
transistor count | 140,000,000 + |
turbo frequency (1 core) | 1,900 MHz (1.9 GHz, 1,900,000 kHz) + |
word size | 32 bit (4 octets, 8 nibbles) + |