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{{core
 
{{core
 
| name              = Tolapai
 
| name              = Tolapai
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| image            = EP80579 QuickAssist.png
 
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| succession      = Yes
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| predecessor      = Stealey
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| predecessor link = intel/cores/stealey
 
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'''Tolapai''' is the codename for Intel's [[embedded]] [[system on a chip]]s based on the {{intel|Pentium M|l=arch}} microarchitecture.
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[[File:EP80579.png|right|thumb]]
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'''Tolapai''' is the core for Intel's {{intel|EP80579}} [[system on a chip]]s based on the {{intel|Pentium M|l=arch}} microarchitecture.
  
 
== Overview ==
 
== Overview ==
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== Members ==
 
== Members ==
 
{{empty section}}
 
{{empty section}}
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== Die Shot ==
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* [[90 nm process]]
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* 148,000,000 transistors
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[[File:Tolapai die shot.png|800px]]
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== Documents ==
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* [[:File:tolapai soc press briefing.pdf|Press Briefing]]

Latest revision as of 04:10, 3 April 2017

Edit Values
Tolapai
EP80579 QuickAssist.png
General Info
DesignerIntel
ManufacturerIntel
IntroductionAugust 30, 2007 (announced)
Microarchitecture
ISAx86-32
MicroarchitecturePentium M
Word Size
4 octets
8 nibbles
32 bit
Process90 nm
0.09 μm
9.0e-5 mm
TechnologyCMOS
Clock600 MHz - 1,200 MHz
Succession
EP80579.png

Tolapai is the core for Intel's EP80579 system on a chips based on the Pentium M microarchitecture.

Overview[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Common Features[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Members[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Die Shot[edit]

Tolapai die shot.png

Documents[edit]

designerIntel +
first announcedAugust 30, 2007 +
instance ofcore +
isax86-32 +
manufacturerIntel +
microarchitecturePentium M +
nameTolapai +
process90 nm (0.09 μm, 9.0e-5 mm) +
technologyCMOS +
word size32 bit (4 octets, 8 nibbles) +