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Difference between revisions of "intel/atom/z510pt"
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{{intel title|Atom Z510PT}}
 
{{intel title|Atom Z510PT}}
−
{{mpu
+
{{chip
 
| name                = Atom Z510PT
 
| name                = Atom Z510PT
 
| no image            =  
 
| no image            =  
Line 10: Line 10:
 
| model number        = Z510PT
 
| model number        = Z510PT
 
| part number        = CH80566EC005DT
 
| part number        = CH80566EC005DT
−
| part number 1       =  
+
| part number 2       =  
 
| s-spec              = SLGPR
 
| s-spec              = SLGPR
 
| s-spec 2            =  
 
| s-spec 2            =  
Line 51: Line 51:
 
| max cpus            = 1
 
| max cpus            = 1
  
−
| electrical          = Yes
+
 
 
| power              =  
 
| power              =  
 
| average power      = 220 mW
 
| average power      = 220 mW
Line 59: Line 59:
 
| sdp                =  
 
| sdp                =  
 
| tdp                = 2 W
 
| tdp                = 2 W
−
| tjunc min          = 0 °C
+
| tjunc min          = -40 °C
−
| tjunc max          = 90 °C
+
| tjunc max          = 110 °C
 
| tcase min          = -40 °C
 
| tcase min          = -40 °C
 
| tcase max          = 85 °C
 
| tcase max          = 85 °C
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This model is identical to the {{\\|Z510P}} but has an industrial operating temperature range. This processor has a TDP of 2 W when {{intel|Hyper-Threading}} is disabled and 2.2 W when enabled.
 
This model is identical to the {{\\|Z510P}} but has an industrial operating temperature range. This processor has a TDP of 2 W when {{intel|Hyper-Threading}} is disabled and 2.2 W when enabled.
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/bonnell#Memory_Hierarchy|l1=Bonnell § Cache}}
 +
{{cache size
 +
|l1 cache=56 KiB
 +
|l1i cache=32 KiB
 +
|l1i break=1x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=24 KiB
 +
|l1d break=1x24 KiB
 +
|l1d desc=6-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=512 KiB
 +
|l2 break=1x512 KiB
 +
|l2 desc=8-way set associative
 +
}}
 +
 +
== Memory controller ==
 +
This processor has no integrated memory controller.
 +
 +
== Graphics ==
 +
This processor has no integrated graphics.
 +
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=No
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=No
 +
|sse42=No
 +
|sse4a=No
 +
|avx=No
 +
|avx2=No
 +
 +
|abm=No
 +
|tbm=No
 +
|bmi1=No
 +
|bmi2=No
 +
|fma3=No
 +
|fma4=No
 +
|aes=No
 +
|rdrand=No
 +
|sha=No
 +
|xop=No
 +
|adx=No
 +
|clmul=No
 +
|f16c=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=Yes
 +
|vpro=No
 +
|vtx=No
 +
|vtd=No
 +
|ept=No
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
}}
 +
 +
== Die Shot ==
 +
{{see also|intel/microarchitectures/bonnell#Silverthorne|l1=Bonnell § Silverthorne Die}}
 +
* [[45 nm process]]
 +
* 9 metal layers
 +
* 47,212,207 transistors
 +
* 3.1 mm x 7.8 mm
 +
* 24.18 mm² die size
 +
 +
[[File:Silverthorne die shot.jpg|650px]]
 +
 +
 +
[[File:Silverthorne die shot (marked).png|650px]]
 +
 +
== Documents ==
 +
=== Datasheet ===
 +
* [[:File:atom z5xx update addendum.pdf|Intel Atom Processor Z5xx Series Datasheet Addendum and Specification Update Addendum]], January 2011

Latest revision as of 15:14, 13 December 2017

Edit Values
Atom Z510PT
silverthorne (437).png
Silverthorne chip
General Info
DesignerIntel
ManufacturerIntel
Model NumberZ510PT
Part NumberCH80566EC005DT
S-SpecSLGPR
MarketMobile
IntroductionMarch 2, 2009 (announced)
March 2, 2009 (launched)
ShopAmazon
General Specs
FamilyAtom
SeriesZ500
LockedYes
Frequency1,100 MHz
Bus typeFSB
Bus speed100 MHz
Bus rate400 MT/s
Clock multiplier11
CPUID106C2
Microarchitecture
ISAx86-32 (x86)
MicroarchitectureBonnell
PlatformMenlow
ChipsetPoulsbo
Core NameSilverthorne
Core Family6
Core Model28
Core SteppingC0
Process45 nm
Transistors47,212,207
TechnologyCMOS
Die24.18 mm²
7.8 mm × 3.1 mm
Word Size32 bit
Cores1
Threads2
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation (average)220 mW
Power (idle)100 mW
Vcore0.75 V-1.1 V
TDP2 W
Tjunction-40 °C – 110 °C
Tcase-40 °C – 85 °C
Tstorage-40 °C – 85 °C
Packaging
PackageFCBGA-437 (FCBGA)
Dimension22 mm x 22 mm x 1.6 mm
Pin Count437
SocketBGA-437 (BGA)

Z510PT is an ultra-low power 32-bit x86 microprocessor introduced by Intel in early 2009 specifically for Mobile Internet Devices (MID). The Z510PT, which is based on the Bonnell microarchitecture (Silverthorne core), is manufactured on a 45 nm process. This processor operates at 1.1 Ghz with a TDP of 2 W. The MPU features a legacy 400 MT/s front-side bus capable of communicating with the Poulsbo chipset in both low-power CMOS mode as well as normal GTL mode (which also works with other chipsets).

This model is identical to the Z510P but has an industrial operating temperature range. This processor has a TDP of 2 W when Hyper-Threading is disabled and 2.2 W when enabled.

Cache[edit]

Main article: Bonnell § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$56 KiB
57,344 B
0.0547 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L1D$24 KiB
24,576 B
0.0234 MiB
1x24 KiB6-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB8-way set associative 

Memory controller[edit]

This processor has no integrated memory controller.

Graphics[edit]

This processor has no integrated graphics.

Features[edit]

Die Shot[edit]

See also: Bonnell § Silverthorne Die
  • 45 nm process
  • 9 metal layers
  • 47,212,207 transistors
  • 3.1 mm x 7.8 mm
  • 24.18 mm² die size

Silverthorne die shot.jpg


Silverthorne die shot (marked).png

Documents[edit]

Datasheet[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/atom/z510pt&oldid=70399"
Facts about "Atom Z510PT - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Atom Z510PT - Intel#package +
base frequency1,100 MHz (1.1 GHz, 1,100,000 kHz) +
bus rate400 MT/s (0.4 GT/s, 400,000 kT/s) +
bus speed100 MHz (0.1 GHz, 100,000 kHz) +
bus typeFSB +
chipsetPoulsbo +
clock multiplier11 +
core count1 +
core family6 +
core model28 +
core nameSilverthorne +
core steppingC0 +
core voltage (max)1.1 V (11 dV, 110 cV, 1,100 mV) +
core voltage (min)0.75 V (7.5 dV, 75 cV, 750 mV) +
cpuid106C2 +
designerIntel +
die area24.18 mm² (0.0375 in², 0.242 cm², 24,180,000 µm²) +
die length7.8 mm (0.78 cm, 0.307 in, 7,800 µm) +
die width3.1 mm (0.31 cm, 0.122 in, 3,100 µm) +
familyAtom +
first announcedMarch 2, 2009 +
first launchedMarch 2, 2009 +
full page nameintel/atom/z510pt +
has featureHyper-Threading Technology + and Enhanced SpeedStep Technology +
has intel enhanced speedstep technologytrue +
has locked clock multipliertrue +
has simultaneous multithreadingtrue +
instance ofmicroprocessor +
isax86-32 +
isa familyx86 +
l1$ size56 KiB (57,344 B, 0.0547 MiB) +
l1d$ description6-way set associative +
l1d$ size24 KiB (24,576 B, 0.0234 MiB) +
l1i$ description8-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
ldateMarch 2, 2009 +
main imageFile:silverthorne (437).png +
main image captionSilverthorne chip +
manufacturerIntel +
market segmentMobile +
max case temperature358.15 K (85 °C, 185 °F, 644.67 °R) +
max cpu count1 +
max junction temperature383.15 K (110 °C, 230 °F, 689.67 °R) +
max storage temperature358.15 K (85 °C, 185 °F, 644.67 °R) +
microarchitectureBonnell +
min case temperature233.15 K (-40 °C, -40 °F, 419.67 °R) +
min junction temperature233.15 K (-40 °C, -40 °F, 419.67 °R) +
min storage temperature233.15 K (-40 °C, -40 °F, 419.67 °R) +
model numberZ510PT +
nameAtom Z510PT +
packageFCBGA-437 +
part numberCH80566EC005DT +
platformMenlow +
power dissipation (average)0.22 W (220 mW, 2.9502e-4 hp, 2.2e-4 kW) +
power dissipation (idle)0.1 W (100 mW, 1.341e-4 hp, 1.0e-4 kW) +
process45 nm (0.045 μm, 4.5e-5 mm) +
s-specSLGPR +
seriesZ500 +
smp max ways1 +
socketBGA-437 +
tdp2 W (2,000 mW, 0.00268 hp, 0.002 kW) +
technologyCMOS +
thread count2 +
transistor count47,212,207 +
word size32 bit (4 octets, 8 nibbles) +