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Difference between revisions of "intel/atom/z520"
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{{intel title|Atom Z520}}
 
{{intel title|Atom Z520}}
−
{{mpu
+
{{chip
 
| name                = Atom Z520
 
| name                = Atom Z520
 
| no image            =  
 
| no image            =  
Line 10: Line 10:
 
| model number        = Z520
 
| model number        = Z520
 
| part number        = AC80566UE014DW
 
| part number        = AC80566UE014DW
−
| part number 1       =  
+
| part number 2       =  
 
| s-spec              = SLB2H
 
| s-spec              = SLB2H
 
| s-spec 2            =  
 
| s-spec 2            =  
−
| s-spec qs          =  
+
| s-spec qs          = QEQS
 
| market              = Mobile
 
| market              = Mobile
 
| first announced    = April 2, 2008
 
| first announced    = April 2, 2008
Line 19: Line 19:
 
| last order          =  
 
| last order          =  
 
| last shipment      =  
 
| last shipment      =  
−
| release price      =  
+
| release price      = $65
  
 
| family              = Atom
 
| family              = Atom
Line 51: Line 51:
 
| max cpus            = 1
 
| max cpus            = 1
  
−
| electrical          = Yes
+
 
 
| power              =  
 
| power              =  
 
| average power      = 220 mW
 
| average power      = 220 mW
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'''Z520''' is an ultra-low power {{arch|32}} [[x86]] microprocessor introduced by [[Intel]] in early 2008 specifically for Mobile Internet Devices (MID). The Z520, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Silverthorne|l=core}} core), is manufactured on a [[45 nm process]]. This processor operates at 1.33 Ghz with a TDP of just 2 W and an average power of 220 mW. The MPU features a legacy 533 MT/s [[front-side bus]] capable of communicating with the {{intel|Poulsbo|l=chipset}} chipset in both low-power [[CMOS]] mode as well as normal [[GTL]] mode (which also works with other chipsets).
 
'''Z520''' is an ultra-low power {{arch|32}} [[x86]] microprocessor introduced by [[Intel]] in early 2008 specifically for Mobile Internet Devices (MID). The Z520, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Silverthorne|l=core}} core), is manufactured on a [[45 nm process]]. This processor operates at 1.33 Ghz with a TDP of just 2 W and an average power of 220 mW. The MPU features a legacy 533 MT/s [[front-side bus]] capable of communicating with the {{intel|Poulsbo|l=chipset}} chipset in both low-power [[CMOS]] mode as well as normal [[GTL]] mode (which also works with other chipsets).
  
−
This processor has a TDP of 2 W when {{intel|Hyper-Threading}} is disabled and 2.2 W when enabled.
+
This processor has a TDP of 2 W when {{intel|Hyper-Threading}} is disabled and 2.2 W when enabled. Model price includes the {{intel|Poulsbo|chipset|l=chipset}}.
 +
 
 +
== Cache ==
 +
{{main|intel/microarchitectures/bonnell#Memory_Hierarchy|l1=Bonnell § Cache}}
 +
{{cache size
 +
|l1 cache=56 KiB
 +
|l1i cache=32 KiB
 +
|l1i break=1x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=24 KiB
 +
|l1d break=1x24 KiB
 +
|l1d desc=6-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=512 KiB
 +
|l2 break=1x512 KiB
 +
|l2 desc=8-way set associative
 +
}}
 +
 
 +
== Memory controller ==
 +
This processor has no integrated memory controller.
 +
 
 +
== Graphics ==
 +
This processor has no integrated graphics.
 +
 
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=No
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=No
 +
|sse42=No
 +
|sse4a=No
 +
|avx=No
 +
|avx2=No
 +
 
 +
|abm=No
 +
|tbm=No
 +
|bmi1=No
 +
|bmi2=No
 +
|fma3=No
 +
|fma4=No
 +
|aes=No
 +
|rdrand=No
 +
|sha=No
 +
|xop=No
 +
|adx=No
 +
|clmul=No
 +
|f16c=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=Yes
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=No
 +
|ept=No
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
}}
 +
 
 +
== Die Shot ==
 +
{{see also|intel/microarchitectures/bonnell#Silverthorne|l1=Bonnell § Silverthorne Die}}
 +
* [[45 nm process]]
 +
* 9 metal layers
 +
* 47,212,207 transistors
 +
* 3.1 mm x 7.8 mm
 +
* 24.18 mm² die size
 +
 
 +
[[File:Silverthorne die shot.jpg|650px]]
 +
 
 +
 
 +
[[File:Silverthorne die shot (marked).png|650px]]
 +
 
 +
== Documents ==
 +
=== Datasheet ===
 +
* [[:File:atom z5xx.pdf|Intel Atom Processor Z5xx Series Datasheet]], June 2010
 +
* [[:File:atom z5xx update.pdf|Intel Atom Processor Z5xx Series Datasheet Specification Update]], July 2014
 +
 
 +
=== Other ===
 +
* [[:File:atom z5xx product brief.pdf|Atom Z5xx Product Brief]], 2008

Latest revision as of 15:14, 13 December 2017

Edit Values
Atom Z520
silverthorne.png
Silverthorne chip
General Info
DesignerIntel
ManufacturerIntel
Model NumberZ520
Part NumberAC80566UE014DW
S-SpecSLB2H
QEQS (QS)
MarketMobile
IntroductionApril 2, 2008 (announced)
April 2, 2008 (launched)
Release Price$65
ShopAmazon
General Specs
FamilyAtom
SeriesZ500
LockedYes
Frequency1,333.33 MHz
Bus typeFSB
Bus speed133.33 MHz
Bus rate533.33 MT/s
Clock multiplier10
CPUID106C2
Microarchitecture
ISAx86-32 (x86)
MicroarchitectureBonnell
PlatformMenlow
ChipsetPoulsbo
Core NameSilverthorne
Core Family6
Core Model28
Core SteppingC0
Process45 nm
Transistors47,212,207
TechnologyCMOS
Die24.18 mm²
7.8 mm × 3.1 mm
Word Size32 bit
Cores1
Threads2
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation (average)220 mW
Power (idle)100 mW
Vcore0.75 V-1.1 V
SDP960 mW
TDP2 W
Tjunction0 °C – 90 °C
Tcase0 °C – 70 °C
Tstorage-40 °C – 85 °C
Packaging
PackageFCBGA-441 (FCBGA)
Dimension13 mm x 14 mm
Pin Count441
SocketBGA-441 (BGA)

Z520 is an ultra-low power 32-bit x86 microprocessor introduced by Intel in early 2008 specifically for Mobile Internet Devices (MID). The Z520, which is based on the Bonnell microarchitecture (Silverthorne core), is manufactured on a 45 nm process. This processor operates at 1.33 Ghz with a TDP of just 2 W and an average power of 220 mW. The MPU features a legacy 533 MT/s front-side bus capable of communicating with the Poulsbo chipset in both low-power CMOS mode as well as normal GTL mode (which also works with other chipsets).

This processor has a TDP of 2 W when Hyper-Threading is disabled and 2.2 W when enabled. Model price includes the chipset.

Cache[edit]

Main article: Bonnell § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$56 KiB
57,344 B
0.0547 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L1D$24 KiB
24,576 B
0.0234 MiB
1x24 KiB6-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB8-way set associative 

Memory controller[edit]

This processor has no integrated memory controller.

Graphics[edit]

This processor has no integrated graphics.

Features[edit]

Die Shot[edit]

See also: Bonnell § Silverthorne Die
  • 45 nm process
  • 9 metal layers
  • 47,212,207 transistors
  • 3.1 mm x 7.8 mm
  • 24.18 mm² die size

Silverthorne die shot.jpg


Silverthorne die shot (marked).png

Documents[edit]

Datasheet[edit]

Other[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/atom/z520&oldid=70401"
Facts about "Atom Z520 - Intel"
RDF feed
has featureHyper-Threading Technology + and Enhanced SpeedStep Technology +
has intel enhanced speedstep technologytrue +
has simultaneous multithreadingtrue +
l1$ size56 KiB (57,344 B, 0.0547 MiB) +
l1d$ description6-way set associative +
l1d$ size24 KiB (24,576 B, 0.0234 MiB) +
l1i$ description8-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +