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Difference between revisions of "loongson/godson 2/2c"
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{{loongson title|Godson-2C}} | {{loongson title|Godson-2C}} | ||
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| name = Godson-2C | | name = Godson-2C | ||
| image = godson-2c.jpg | | image = godson-2c.jpg | ||
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| model number = 2C | | model number = 2C | ||
| part number = DXP100 | | part number = DXP100 | ||
| − | | part number | + | | part number 2 = |
| market = Desktop | | market = Desktop | ||
| first announced = 2004 | | first announced = 2004 | ||
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| max memory = | | max memory = | ||
| − | + | ||
| power = 5 W | | power = 5 W | ||
| v core = | | v core = | ||
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| socket 0 type = | | socket 0 type = | ||
}} | }} | ||
| − | '''Godson-2C''' ('''龙芯2C''') is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in late [[2004]], the Godson-2C operates at up to 500 MHz consuming 3-5W. This chip was manufactured on [[SMICS]]' [[0.18 µm process]]. | + | '''Godson-2C''' ('''龙芯2C''') is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in late [[2004]], the Godson-2C operates at up to 500 MHz consuming 3-5W. This chip was manufactured on [[SMICS]]' [[0.18 µm process]]. This chip reached tapeout on June 8, 2004. |
The Godson-2C provides roughly three times the performance of {{\\|2B}}. The 2C has twice the cache and almost twice the frequency as the {{\\|2B}}, along with an improved [[branch predictor]]. | The Godson-2C provides roughly three times the performance of {{\\|2B}}. The 2C has twice the cache and almost twice the frequency as the {{\\|2B}}, along with an improved [[branch predictor]]. | ||
| + | |||
| + | Loongson has claimed the Godson-2C has reached the performance level of 500-800 MHz {{intel|PIII}} based on their SPECint2000 scores. | ||
== Cache == | == Cache == | ||
{{main|loongson/microarchitectures/GS464#Memory_Hierarchy|l1=GS464 § Cache}} | {{main|loongson/microarchitectures/GS464#Memory_Hierarchy|l1=GS464 § Cache}} | ||
| + | This chip was typically combined with 1 MiB - 8 MiB [[L2 cache]] off-die (on the motherboard). | ||
{{cache size | {{cache size | ||
|l1 cache=128 KiB | |l1 cache=128 KiB | ||
| Line 105: | Line 108: | ||
|l1d policy= | |l1d policy= | ||
}} | }} | ||
| + | |||
| + | == References == | ||
| + | * Hu, Wei-Wu, and Jian Wang. "Making effective decisions in computer architects’ real-world: Lessons and experiences with Godson-2 processor designs." Journal of Computer Science and Technology 23.4 (2008): 620-632. | ||
Latest revision as of 15:31, 13 December 2017
| Edit Values | |
| Godson-2C | |
 | |
| Godson-2C chip | |
| General Info | |
| Designer | Loongson |
| Manufacturer | SMICS |
| Model Number | 2C |
| Part Number | DXP100 |
| Market | Desktop |
| Introduction | 2004 (announced) September 28, 2004 (launched) |
| General Specs | |
| Family | Godson 2 |
| Series | Godson 2 |
| Frequency | 500 MHz |
| Microarchitecture | |
| ISA | MIPS64 (MIPS) |
| Microarchitecture | GS464 |
| Core Name | GS464 |
| Process | 180 nm |
| Transistors | 13,500,000 |
| Technology | CMOS |
| Die | 41.54 mm² 6,200 µm × 6,700 µm |
| Word Size | 64 bit |
| Cores | 1 |
| Threads | 1 |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 5 W |
Godson-2C (龙芯2C) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in late 2004, the Godson-2C operates at up to 500 MHz consuming 3-5W. This chip was manufactured on SMICS' 0.18 µm process. This chip reached tapeout on June 8, 2004.
The Godson-2C provides roughly three times the performance of 2B. The 2C has twice the cache and almost twice the frequency as the 2B, along with an improved branch predictor.
Loongson has claimed the Godson-2C has reached the performance level of 500-800 MHz PIII based on their SPECint2000 scores.
Cache[edit]
- Main article: GS464 § Cache
This chip was typically combined with 1 MiB - 8 MiB L2 cache off-die (on the motherboard).
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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References[edit]
- Hu, Wei-Wu, and Jian Wang. "Making effective decisions in computer architects’ real-world: Lessons and experiences with Godson-2 processor designs." Journal of Computer Science and Technology 23.4 (2008): 620-632.
Facts about "Godson-2C - Loongson"
| base frequency | 500 MHz (0.5 GHz, 500,000 kHz) + |
| core count | 1 + |
| core name | GS464 + |
| designer | Loongson + |
| die area | 41.54 mm² (0.0644 in², 0.415 cm², 41,540,000 µm²) + |
| die length | 6.2 mm (0.62 cm, 0.244 in, 6,200 µm) + |
| die width | 6.7 mm (0.67 cm, 0.264 in, 6,700 µm) + |
| family | Godson 2 + |
| first announced | 2004 + |
| first launched | September 28, 2004 + |
| full page name | loongson/godson 2/2c + |
| instance of | microprocessor + |
| isa | MIPS64 + |
| isa family | MIPS + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| ldate | September 28, 2004 + |
| main image |  + |
| main image caption | Godson-2C chip + |
| manufacturer | SMICS + |
| market segment | Desktop + |
| max cpu count | 1 + |
| microarchitecture | GS464 + |
| model number | 2C + |
| name | Godson-2C + |
| part number | DXP100 + |
| power dissipation | 5 W (5,000 mW, 0.00671 hp, 0.005 kW) + |
| process | 180 nm (0.18 μm, 1.8e-4 mm) + |
| series | Godson 2 + |
| smp max ways | 1 + |
| technology | CMOS + |
| thread count | 1 + |
| transistor count | 13,500,000 + |
| word size | 64 bit (8 octets, 16 nibbles) + |
