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Difference between revisions of "xiaomi/surge/s1"
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{{xiaomi title|Surge S1}} | {{xiaomi title|Surge S1}} | ||
| − | {{ | + | {{chip |
| future = Yes | | future = Yes | ||
| name = Xiaomi Surge S1 | | name = Xiaomi Surge S1 | ||
| Line 12: | Line 12: | ||
| model number = S1 | | model number = S1 | ||
| part number = | | part number = | ||
| − | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Mobile | | market = Mobile | ||
| first announced = February 28, 2017 | | first announced = February 28, 2017 | ||
| Line 93: | Line 93: | ||
| socket 0 type = | | socket 0 type = | ||
}} | }} | ||
| − | '''Surge S1''' is a {{arch|64}} [[octa-core]] performance [[ARM]] system-on-chip designed by [[Xiaomi]] and introduced in early [[2017]]. This chip incorporates 8 {{armh|Cortex-A53}} cores in a {{armh|big.LITTLE}} configuration with four cores operating at up to 2.2 GHz with the other four set of cores operating at 1.4 GHz. This processor is fabricated on TSMC's [[28 nm process|28 nm HPC+ process]] and incorporates a {{armh|Mali-T860}} [[IGP]]. | + | [[File:surge s1 dev roadmap.jpg|thumb|right]] |
| + | [[File:surge s1 block.jpg|400px|right]] | ||
| + | '''Surge S1''' is a {{arch|64}} [[octa-core]] performance [[ARM]] system-on-chip designed by [[Xiaomi]] and introduced in early [[2017]]. This chip incorporates 8 {{armh|Cortex-A53}} cores in a {{armh|big.LITTLE}} configuration with four cores operating at up to 2.2 GHz with the other four set of cores operating at 1.4 GHz. This processor is fabricated on TSMC's [[28 nm process|28 nm HPC+ process]] and incorporates a {{armh|Mali-T860}} MP4 [[IGP]]. The S1 is Xiaomi's first generation in-house developed system-on-chip. | ||
{{unknown features}} | {{unknown features}} | ||
| + | |||
| + | |||
| + | == Memory controller == | ||
| + | {{memory controller | ||
| + | |type=LPDDR3-1866 | ||
| + | |ecc=No | ||
| + | |controllers=1 | ||
| + | |channels=2 | ||
| + | |width=32 bit | ||
| + | |max bandwidth=13.91 GiB/s | ||
| + | |bandwidth schan=6.95 | ||
| + | |bandwidth dchan=13.91 GiB/s | ||
| + | }} | ||
== Graphics == | == Graphics == | ||
| Line 110: | Line 125: | ||
| output dsi = Yes | | output dsi = Yes | ||
| − | | max res dsi = | + | | max res dsi = 2560×1600 |
| direct3d ver = 11.2 | | direct3d ver = 11.2 | ||
| Line 119: | Line 134: | ||
| openvg ver = 1.1 | | openvg ver = 1.1 | ||
}} | }} | ||
| + | |||
| + | == Image == | ||
| + | * AFBC + ASTC | ||
| + | * 14-bit dual ISP | ||
| + | |||
| + | == Video == | ||
| + | * Video capturing 4K@30fps, 1080p@120fps, 720p@240/fps | ||
| + | * H.265/HEVC (Main profile) | ||
| + | * H.264 (Baseline/Main/High profile) | ||
| + | * MPEG4 (Simple profile/ASP), | ||
| + | * VC-1(Simple/Main/Advanced profile) | ||
== Utilizing devices == | == Utilizing devices == | ||
| − | * [[used by::Xiaomi Mi 5C]] | + | * [[used by::Xiaomi Mi 5C, Cubepilot HereLink]] |
| − | |||
{{expand list}} | {{expand list}} | ||
Latest revision as of 03:42, 7 April 2022
| Edit Values | |
| Xiaomi Surge S1 | |
| General Info | |
| Designer | Xiaomi, ARM Holdings |
| Manufacturer | TSMC |
| Model Number | S1 |
| Market | Mobile |
| Introduction | February 28, 2017 (announced) |
| General Specs | |
| Family | Surge |
| Frequency | 1,400 MHz, 2,200 MHz |
| Bus type | AXI |
| Microarchitecture | |
| ISA | ARMv8 (ARM) |
| Microarchitecture | Cortex-A53 |
| Core Name | Cortex-A53 |
| Process | 28 nm |
| Technology | CMOS |
| Cores | 8 |
| Threads | 8 |
Surge S1 is a 64-bit octa-core performance ARM system-on-chip designed by Xiaomi and introduced in early 2017. This chip incorporates 8 Cortex-A53 cores in a big.LITTLE configuration with four cores operating at up to 2.2 GHz with the other four set of cores operating at 1.4 GHz. This processor is fabricated on TSMC's 28 nm HPC+ process and incorporates a Mali-T860 MP4 IGP. The S1 is Xiaomi's first generation in-house developed system-on-chip.
 |
Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Memory controller[edit]
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Integrated Memory Controller
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Graphics[edit]
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Integrated Graphics Information
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Image[edit]
- AFBC + ASTC
- 14-bit dual ISP
Video[edit]
- Video capturing 4K@30fps, 1080p@120fps, 720p@240/fps
- H.265/HEVC (Main profile)
- H.264 (Baseline/Main/High profile)
- MPEG4 (Simple profile/ASP),
- VC-1(Simple/Main/Advanced profile)
Utilizing devices[edit]
- Xiaomi Mi 5C, Cubepilot HereLink
This list is incomplete; you can help by expanding it.
Facts about "Surge S1 - Xiaomi"
| base frequency | 1,400 MHz (1.4 GHz, 1,400,000 kHz) + and 2,200 MHz (2.2 GHz, 2,200,000 kHz) + |
| bus type | AXI + |
| core count | 8 + |
| core name | Cortex-A53 + |
| designer | Xiaomi + and ARM Holdings + |
| family | Surge + |
| first announced | February 28, 2017 + |
| full page name | xiaomi/surge/s1 + |
| has ecc memory support | false + |
| instance of | microprocessor + |
| integrated gpu | Mali-T860 + |
| integrated gpu base frequency | 800 MHz (0.8 GHz, 800,000 KHz) + |
| integrated gpu designer | ARM Holdings + |
| integrated gpu execution units | 4 + |
| isa | ARMv8 + |
| isa family | ARM + |
| ldate | 3000 + |
| manufacturer | TSMC + |
| market segment | Mobile + |
| max memory bandwidth | 13.91 GiB/s (14,243.84 MiB/s, 14.936 GB/s, 14,935.749 MB/s, 0.0136 TiB/s, 0.0149 TB/s) + |
| max memory channels | 2 + |
| microarchitecture | Cortex-A53 + |
| model number | S1 + |
| name | Xiaomi Surge S1 + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |
| supported memory type | LPDDR3-1866 + |
| technology | CMOS + |
| thread count | 8 + |
| used by | Xiaomi Mi 5C, Cubepilot HereLink + |