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Difference between revisions of "cavium/octeon plus/cn5830-600bg1521-exp"
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{{cavium title|CN5830-600 EXP}} | {{cavium title|CN5830-600 EXP}} | ||
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| name = Cavium CN5830-600 EXP | | name = Cavium CN5830-600 EXP | ||
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| model number = CN5830-600 EXP | | model number = CN5830-600 EXP | ||
| part number = CN5830-600BG1521-EXP | | part number = CN5830-600BG1521-EXP | ||
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| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Network | | market = Network | ||
| first announced = October 9, 2006 | | first announced = October 9, 2006 | ||
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| core model = | | core model = | ||
| core stepping = | | core stepping = | ||
| − | | process = | + | | process = 90 nm |
| transistors = | | transistors = | ||
| technology = CMOS | | technology = CMOS | ||
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| max memory addr = | | max memory addr = | ||
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| power = 15 W | | power = 15 W | ||
| v core = | | v core = | ||
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| − | + | |package module 1={{packages/cavium/fcbga-1521}} | |
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}} | }} | ||
| + | '''CN5830-600 EXP''' is a {{arch|64}} [[quad-core]] [[MIPS]] network microprocessor designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates four {{cavium|cnMIPS|l=arch}} cores, operates at 600 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as [[RegEx]], compression/decompression, and TCP acceleration. | ||
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|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
}} | }} | ||
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| + | == Memory controller == | ||
| + | {{memory controller | ||
| + | |type=DDR2-800 | ||
| + | |ecc=Yes | ||
| + | |max mem= | ||
| + | |controllers=1 | ||
| + | |channels=1 | ||
| + | |width=128 bit | ||
| + | |max bandwidth=11.92 GiB/s | ||
| + | |bandwidth schan=11.92 GiB/s | ||
| + | }} | ||
| + | |||
| + | == Expansions == | ||
| + | {{expansions | ||
| + | |pcix width=64 bit | ||
| + | |pcix clock=133.33 MHz | ||
| + | |pcix rate=1,017.25 MiB/s | ||
| + | |pcix extra=host or slave | ||
| + | |uart=yes | ||
| + | |uart ports=2 | ||
| + | |gp io=Yes | ||
| + | }} | ||
| + | |||
| + | == Networking == | ||
| + | {{network | ||
| + | |mii opts=Yes | ||
| + | |rgmii=yes | ||
| + | |rgmii ports=8 | ||
| + | |spi opts=Yes | ||
| + | |spi42=Yes | ||
| + | |spi42 ports=2 | ||
| + | }} | ||
| + | |||
| + | == Hardware Accelerators == | ||
| + | {{accelerators | ||
| + | |regex=Yes | ||
| + | |regex feature=32 Engines | ||
| + | |compression=Yes | ||
| + | |decompression=Yes | ||
| + | |tcp=Yes | ||
| + | |qos=Yes | ||
| + | }} | ||
| + | |||
| + | == Block diagram == | ||
| + | [[File:octeon plus cn58xx.png|750px]] | ||
| + | |||
| + | == Datasheet == | ||
| + | * [[:File:octeon plus cn58xx (rev 1.4).pdf|OCTEON CN58XX Processors Product Brief]] | ||
Latest revision as of 15:12, 13 December 2017
| Edit Values | |||||||
| Cavium CN5830-600 EXP | |||||||
 | |||||||
| General Info | |||||||
| Designer | Cavium | ||||||
| Manufacturer | TSMC | ||||||
| Model Number | CN5830-600 EXP | ||||||
| Part Number | CN5830-600BG1521-EXP | ||||||
| Market | Network | ||||||
| Introduction | October 9, 2006 (announced) February, 2007 (launched) | ||||||
| General Specs | |||||||
| Family | OCTEON Plus | ||||||
| Series | CN58xx | ||||||
| Frequency | 600 MHz | ||||||
| Microarchitecture | |||||||
| ISA | MIPS64 (MIPS) | ||||||
| Microarchitecture | cnMIPS | ||||||
| Process | 90 nm | ||||||
| Technology | CMOS | ||||||
| Word Size | 64 bit | ||||||
| Cores | 4 | ||||||
| Threads | 4 | ||||||
| Multiprocessing | |||||||
| Max SMP | 1-Way (Uniprocessor) | ||||||
| Electrical | |||||||
| Power dissipation | 15 W | ||||||
| Packaging | |||||||
| |||||||
CN5830-600 EXP is a 64-bit quad-core MIPS network microprocessor designed by Cavium and introduced in 2007. This processor, which incorporates four cnMIPS cores, operates at 600 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of various software such as RegEx, compression/decompression, and TCP acceleration.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Networking[edit]
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Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
Facts about "CN5830-600 EXP - Cavium"
