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Difference between revisions of "mediatek/helio/mt6795t"
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(→‎Graphics)
(I have added one more model that i am using on this chip)
 
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{{mediatek title|Helio X10 (MT6795T)}}
+
{{mediatek title|Helio X10 T (MT6795T)}}
−
{{mpu
+
{{chip
−
| name                = MediaTek Helio X10
+
| name                = MediaTek Helio X10 T
 
| no image            = yes
 
| no image            = yes
 
| image              =  
 
| image              =  
Line 9: Line 9:
 
| designer 2          = ARM Holdings
 
| designer 2          = ARM Holdings
 
| manufacturer        = TSMC
 
| manufacturer        = TSMC
−
| model number        = Helio X10
+
| model number        = Helio X10 T
 
| part number        = MT6795T
 
| part number        = MT6795T
 +
| part number 2      = MTK6795T
 
| market              = Mobile
 
| market              = Mobile
 
| market 2            = Embedded
 
| market 2            = Embedded
Line 50: Line 51:
 
| max memory          = 4 GiB
 
| max memory          = 4 GiB
  
−
| electrical          = Yes
+
 
 
| power              =  
 
| power              =  
 
| v core              = 1 V
 
| v core              = 1 V
Line 84: Line 85:
 
| package 0 height    = 0.78 mm
 
| package 0 height    = 0.78 mm
 
}}
 
}}
−
'''Helio X10''' ('''MT6795T''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in early-[[2014]]. This SoC, which incorporates eight {{armh|Cortex-A53}} cores and is manufactured on TSMC's [[28 nm process]], operates at up to 2.2 GHz and supports dual-channel LPDDR3-933. This chip incorporates the {{imgtec|PowerVR G6200}} [[IGP]] operating at 700 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 4.
+
'''Helio X10 T''' ('''MT6795T'''; T for ''turbo'') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in early-[[2015]]. This SoC, which incorporates eight {{armh|Cortex-A53}} cores and is manufactured on TSMC's [[28 nm process]], operates at up to 2.2 GHz and supports dual-channel LPDDR3-1866. This chip incorporates the {{imgtec|PowerVR G6200}} [[IGP]] operating at 700 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 4. This "turbo" variant of the X10 operates at 10% higher frequency.
  
 
This SoC is made of 2 clusters of 4-core each ({{armh|Cortex-A53}}) linked together via a {{armh|CCI-400}}, a {{armh|NEON}} engine, and {{armh|Cortex-R4}} core for the second MCU subsystem.
 
This SoC is made of 2 clusters of 4-core each ({{armh|Cortex-A53}}) linked together via a {{armh|CCI-400}}, a {{armh|NEON}} engine, and {{armh|Cortex-R4}} core for the second MCU subsystem.
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== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
−
|type=DDR3-933
+
|type=LPDDR3-1866
 
|ecc=No
 
|ecc=No
 
|max mem=4 GiB
 
|max mem=4 GiB
 
|controllers=1
 
|controllers=1
 
|channels=2
 
|channels=2
−
|max bandwidth=13.9 GiB/s
+
|width=32 bit
 +
|max bandwidth=13.91 GiB/s
 
|bandwidth schan=6.95 GiB/s
 
|bandwidth schan=6.95 GiB/s
−
|bandwidth dchan=13.9 GiB/s
+
|bandwidth dchan=13.91 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions
 +
|usb revision=2.0
 +
|usb revision 2=3.0
 +
|usb ports=8
 +
|uart=4
 +
|gp io=Yes
 
}}
 
}}
  
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| opencl ver          = 1.2
 
| opencl ver          = 1.2
 
| opengl ver          = 3.2
 
| opengl ver          = 3.2
−
| opencl es ver      = 3.1
+
| opengl es ver      = 3.1
 
| vulkan ver          = 1.0
 
| vulkan ver          = 1.0
 
}}
 
}}
 +
 +
* OpenGL ES 3.0 3D graphic accelerator capable of processing 175M tri/sec and 2,800M pixel/sec  @ 700 MHz
 +
* OpenVG 1.1 vector graphics accelerator
  
 
== Wireless ==
 
== Wireless ==
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| 2g                = Yes
 
| 2g                = Yes
 
| csd              = Yes
 
| csd              = Yes
−
| gsm              =  
+
| gsm              = Yes
 
| gprs              = Yes
 
| gprs              = Yes
 
| edge              = Yes
 
| edge              = Yes
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| ue cat            = 4
 
| ue cat            = 4
 
}}
 
}}
 +
 +
== Image ==
 +
* Integrated image signal processor supports 20 MP
 +
* Supports image stabilization
 +
* Supports video stabilization
 +
* Supports noise reduction
 +
* Supports lens shading correction
 +
* Supports AE/AWB/AF
 +
* Supports edge enhancement
 +
* Supports face detection and visual tracking
 +
* Hardware JPEG encoder
 +
 +
== Video ==
 +
* HEVC decoder 4k2k @ 30fps
 +
* H.264 decoder (30fps/40Mbps)
 +
* Sorenson H.263/H.263 decoder (1080p @ 60fps/40Mbps)
 +
* MPEG-4 SP/ASP decoder (1080p @ 60fps/40Mbps)
 +
* DIVX4/DIVX5/DIVX6/DIVX HD/XVID decoder  (1080p @ 60fps/40Mbps)
 +
* VP8 / VC-1 decoders
 +
* MPEG-4 / H.263 / H.264 / HEVC encoders
 +
 +
== Audio ==
 +
* Audio content sampling rates 8kHz to 192kHz
 +
* Audio content sampling format 8-bit/16-bit/24-bit Mono/Stereo
 +
* I2S, PCM
 +
* Encode: AMR-NB, AMR-WB, AAC, OGG, ADPCM
 +
* Decode: WAV, MP3, MP2, AAC, AMR-NB, AMR-WB, MIDI, Vorbis, APE, AAC-plus v1, AAC-plus v2, FLAC, WMA, ADPCM
 +
* 7.1 channel MHL output
 +
 +
== Utilizing devices ==
 +
* [[used by::Meizu MX5]]
 +
* [[used by::LeEco Le 1s]]
 +
* [[used by::Xiaomi Redmi Note 2]]
 +
* [[used by::HTC One X9]]
 +
* [[used by::HTC One M9+]]
 +
* [[used by::HTC One ME]]
 +
 +
{{expand list}}

Latest revision as of 08:36, 22 August 2018

Edit Values
MediaTek Helio X10 T
General Info
DesignerMediaTek,
ARM Holdings
ManufacturerTSMC
Model NumberHelio X10 T
Part NumberMT6795T,
MTK6795T
MarketMobile, Embedded
IntroductionJuly 15, 2014 (announced)
March 27, 2015 (launched)
General Specs
FamilyHelio
SeriesHelio X
Frequency2,200 MHz
Bus typeAMBA 4 AXI
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A53
Core NameCortex-A53
Process28 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Max Memory4 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1 V
VI/O1.8 V, 2.8 V, 3.3 V
OP Temperature-20 °C – 80 °C
Tjunction – 125 °C
Tstorage0 °C – 125 °C

Helio X10 T (MT6795T; T for turbo) is a 64-bit octa-core ARM LTE system on a chip designed by MediaTek and introduced in early-2015. This SoC, which incorporates eight Cortex-A53 cores and is manufactured on TSMC's 28 nm process, operates at up to 2.2 GHz and supports dual-channel LPDDR3-1866. This chip incorporates the PowerVR G6200 IGP operating at 700 MHz. This SoC has a modem supporting LTE User Equipment (UE) category 4. This "turbo" variant of the X10 operates at 10% higher frequency.

This SoC is made of 2 clusters of 4-core each (Cortex-A53) linked together via a CCI-400, a NEON engine, and Cortex-R4 core for the second MCU subsystem.

Cache[edit]

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB2-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB4-way set associative 
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB16-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR3-1866
Supports ECCNo
Max Mem4 GiB
Controllers1
Channels2
Width32 bit
Max Bandwidth13.91 GiB/s
14,243.84 MiB/s
14.936 GB/s
14,935.749 MB/s
0.0136 TiB/s
0.0149 TB/s
Bandwidth
Single 6.95 GiB/s
Double 13.91 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0, 3.0
Ports8
UART
GP I/OYes


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR G6200
DesignerImagination Technologies
Max Displays2
Frequency700 MHz
0.7 GHz
700,000 KHz
OutputDSI
Max Resolution
DSI2560x1600
Standards
Direct3D10.0
OpenGL3.2
OpenCL1.2
OpenGL ES3.1
Vulkan1.0
  • OpenGL ES 3.0 3D graphic accelerator capable of processing 175M tri/sec and 2,800M pixel/sec @ 700 MHz
  • OpenVG 1.1 vector graphics accelerator

Wireless[edit]

Antu network-wireless-connected-100.svgWireless Communications
Cellular
2G
CSD Yes
GSM Yes
GPRS Yes
EDGE Yes
3G
UMTS
TD-SCDMAYes
DC-HSDPAYes
HSUPAYes
4G
LTE Advanced
E-UTRANYes
UE Cat4

Image[edit]

  • Integrated image signal processor supports 20 MP
  • Supports image stabilization
  • Supports video stabilization
  • Supports noise reduction
  • Supports lens shading correction
  • Supports AE/AWB/AF
  • Supports edge enhancement
  • Supports face detection and visual tracking
  • Hardware JPEG encoder

Video[edit]

  • HEVC decoder 4k2k @ 30fps
  • H.264 decoder (30fps/40Mbps)
  • Sorenson H.263/H.263 decoder (1080p @ 60fps/40Mbps)
  • MPEG-4 SP/ASP decoder (1080p @ 60fps/40Mbps)
  • DIVX4/DIVX5/DIVX6/DIVX HD/XVID decoder (1080p @ 60fps/40Mbps)
  • VP8 / VC-1 decoders
  • MPEG-4 / H.263 / H.264 / HEVC encoders

Audio[edit]

  • Audio content sampling rates 8kHz to 192kHz
  • Audio content sampling format 8-bit/16-bit/24-bit Mono/Stereo
  • I2S, PCM
  • Encode: AMR-NB, AMR-WB, AAC, OGG, ADPCM
  • Decode: WAV, MP3, MP2, AAC, AMR-NB, AMR-WB, MIDI, Vorbis, APE, AAC-plus v1, AAC-plus v2, FLAC, WMA, ADPCM
  • 7.1 channel MHL output

Utilizing devices[edit]

  • Meizu MX5
  • LeEco Le 1s
  • Xiaomi Redmi Note 2
  • HTC One X9
  • HTC One M9+
  • HTC One ME

This list is incomplete; you can help by expanding it.

Retrieved from "https://en.wikichip.org/w/index.php?title=mediatek/helio/mt6795t&oldid=81718"
Facts about "Helio X10 T (MT6795T) - MediaTek"
RDF feed
has 2g supporttrue +
has 3g supporttrue +
has 4g supporttrue +
has csd supporttrue +
has dc-hsdpa supporttrue +
has e-utran supporttrue +
has ecc memory supportfalse +
has edge supporttrue +
has gprs supporttrue +
has hsupa supporttrue +
has lte advanced supporttrue +
has td-scdma supporttrue +
has umts supporttrue +
integrated gpuPowerVR G6200 +
integrated gpu base frequency700 MHz (0.7 GHz, 700,000 KHz) +
integrated gpu designerImagination Technologies +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description4-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description2-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description16-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth13.9 GiB/s (14,233.6 MiB/s, 14.925 GB/s, 14,925.011 MB/s, 0.0136 TiB/s, 0.0149 TB/s) +
max memory channels2 +
supported memory typeDDR3-933 +
user equipment category4 +