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Difference between revisions of "intel/core i7ee/i7-940xm"
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{{intel title|Core i7-940XM Extreme Edition}} | {{intel title|Core i7-940XM Extreme Edition}} | ||
− | {{ | + | {{chip |
| name = Core i7-940XM Extreme Edition | | name = Core i7-940XM Extreme Edition | ||
| no image = Yes | | no image = Yes | ||
Line 12: | Line 12: | ||
| market = Mobile | | market = Mobile | ||
| first announced = February 5, 2010 | | first announced = February 5, 2010 | ||
− | | first launched = June | + | | first launched = June 22, 2010 |
| last order = September 30, 2011 | | last order = September 30, 2011 | ||
| last shipment = December, 2011 | | last shipment = December, 2011 | ||
Line 20: | Line 20: | ||
| series = Core i7-900 | | series = Core i7-900 | ||
| locked = No | | locked = No | ||
− | | frequency = | + | | frequency = 2,133.33 MHz |
| turbo frequency = Yes | | turbo frequency = Yes | ||
− | | turbo frequency1 = | + | | turbo frequency1 = 3,333.33 MHz |
− | | turbo frequency2 = | + | | turbo frequency2 = 3,199.99 MHz |
− | | turbo frequency3 = | + | | turbo frequency3 = 2,399.99 MHz |
− | | turbo frequency4 = | + | | turbo frequency4 = 2,399.99 MHz |
| bus type = DMI | | bus type = DMI | ||
| bus speed = | | bus speed = | ||
Line 38: | Line 38: | ||
| microarch = Nehalem | | microarch = Nehalem | ||
| platform = Calpella | | platform = Calpella | ||
+ | | chipset = Ibex Peak | ||
| core name = Clarksfield | | core name = Clarksfield | ||
+ | | core family = 6 | ||
+ | | core model = 30 | ||
| core stepping = B1 | | core stepping = B1 | ||
| process = 45 nm | | process = 45 nm | ||
Line 50: | Line 53: | ||
| thread count = 8 | | thread count = 8 | ||
| max cpus = 1 | | max cpus = 1 | ||
− | | max memory = 8 | + | | max memory = 8 GiB |
+ | |||
− | |||
| power = | | power = | ||
| sdp = | | sdp = | ||
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| socket type = | | socket type = | ||
}} | }} | ||
− | The '''Core i7-940XM {{intel|Core i7EE|Extreme Edition}}''' is a {{arch|64}} quad-core [[microprocessor]] introduced by [[Intel]] in early 2010 for the mobile market. The Core i7-940XM EE, which operated at 2.13 GHz with turbo frequency of up to 3.33 GHz for a single core was Intel's flagship mobile processor for the {{intel|Nehalem}} [[microarchitecture]]. The 940XM is identical to the {{\\|i7-920XM}} | + | The '''Core i7-940XM {{intel|Core i7EE|Extreme Edition}}''' is a {{arch|64}} quad-core [[microprocessor]] introduced by [[Intel]] in early 2010 for the mobile market. The Core i7-940XM EE, which operated at 2.13 GHz with turbo frequency of up to 3.33 GHz for a single core was Intel's flagship mobile processor for the {{intel|Nehalem}} [[microarchitecture]]. The 940XM is identical to the {{\\|i7-920XM}} aside from a slightly higer base/Turbo clock speed. The chip is manufactured in [[45 nm process]]. The i7-940XM supports 8GB of memory and has a thermal design power of 55 W. |
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/nehalem#Memory_Hierarchy|l1=Nehalem | + | {{main|intel/microarchitectures/nehalem#Memory_Hierarchy|l1=Nehalem § Cache}} |
− | {{cache | + | {{cache size |
+ | |l1 cache=256 KiB | ||
|l1i cache=128 KiB | |l1i cache=128 KiB | ||
|l1i break=4x32 KiB | |l1i break=4x32 KiB | ||
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
− | |l1i | + | |l1i policy=write-back |
|l1d cache=128 KiB | |l1d cache=128 KiB | ||
|l1d break=4x32 KiB | |l1d break=4x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
− | |l1d | + | |l1d policy=write-back |
|l2 cache=1 MiB | |l2 cache=1 MiB | ||
|l2 break=4x256 KiB | |l2 break=4x256 KiB | ||
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
− | |l2 | + | |l2 policy=write-back |
|l3 cache=8 MiB | |l3 cache=8 MiB | ||
+ | |l3 break=4x2 MiB | ||
|l3 desc=16-way set associative | |l3 desc=16-way set associative | ||
− | |l3 | + | |l3 policy=write-back |
}} | }} | ||
== Memory controller == | == Memory controller == | ||
− | {{ | + | {{memory controller |
− | | type | + | |type=DDR3-1333 |
− | + | |controllers=1 | |
− | | controllers | + | |channels=2 |
− | | channels | + | |ecc=no |
− | | ecc | + | |max bandwidth=19.87 GiB/s |
− | | max bandwidth | + | |max mem=8 GiB |
− | | bandwidth schan | + | |bandwidth schan=9.93 GiB/s |
− | | bandwidth dchan | + | |bandwidth dchan=19.87 GiB/s |
− | | | + | |pae=36 bit |
}} | }} | ||
Line 105: | Line 110: | ||
== Expansions == | == Expansions == | ||
− | {{ | + | {{expansions |
| pcie revision = 2.0 | | pcie revision = 2.0 | ||
| pcie lanes = 16 | | pcie lanes = 16 | ||
| pcie config = 1x16 | | pcie config = 1x16 | ||
− | | pcie config | + | | pcie config 2 = 2x8 |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
}} | }} | ||
== Features == | == Features == | ||
− | {{ | + | {{x86 features |
− | | | + | |real=Yes |
− | | | + | |protected=Yes |
− | | | + | |smm=Yes |
− | | | + | |fpu=Yes |
− | | | + | |x8616=Yes |
− | | | + | |x8632=Yes |
− | | | + | |x8664=Yes |
− | | | + | |nx=Yes |
− | | | + | |3dnow=No |
− | | | + | |e3dnow=No |
− | | | + | |mmx=Yes |
− | | | + | |emmx=Yes |
− | | sse | + | |sse=Yes |
− | | sse2 | + | |sse2=Yes |
− | | sse3 | + | |sse3=Yes |
− | | ssse3 | + | |ssse3=Yes |
− | | | + | |sse41=Yes |
− | | | + | |sse42=Yes |
− | | | + | |sse4a=No |
− | | | + | |avx=No |
− | | | + | |avx2=No |
− | | | + | |
− | | | + | |abm=No |
− | | bmi1 | + | |tbm=No |
− | | bmi2 | + | |bmi1=No |
− | | f16c | + | |bmi2=No |
− | | | + | |fma3=No |
− | | | + | |fma4=No |
− | | eist | + | |aes=No |
− | | | + | |rdrand=No |
− | | | + | |sha=No |
+ | |xop=No | ||
+ | |adx=No | ||
+ | |clmul=No | ||
+ | |f16c=No | ||
+ | |tbt1=Yes | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |flex=No | ||
+ | |isrt=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=No | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=No | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdv=No | ||
+ | |rvi=No | ||
}} | }} | ||
== See also == | == See also == | ||
* {{intel|Core i7EE|Core i7 Extreme Edition}} | * {{intel|Core i7EE|Core i7 Extreme Edition}} |
Latest revision as of 14:01, 13 December 2019
Edit Values | |
Core i7-940XM Extreme Edition | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | i7-940XM |
Part Number | BY80607002526AE |
S-Spec | SLBSC Q4AP (QS) |
Market | Mobile |
Introduction | February 5, 2010 (announced) June 22, 2010 (launched) |
End-of-life | September 30, 2011 (last order) December, 2011 (last shipment) |
Release Price | $1096.00 |
Shop | Amazon |
General Specs | |
Family | Core i7EE |
Series | Core i7-900 |
Locked | No |
Frequency | 2,133.33 MHz |
Turbo Frequency | Yes |
Turbo Frequency | 3,333.33 MHz (1 core), 3,199.99 MHz (2 cores), 2,399.99 MHz (3 cores), 2,399.99 MHz (4 cores) |
Bus type | DMI |
Bus rate | 2.5 GT/s |
Clock multiplier | 16 |
CPUID | 106E5 |
Microarchitecture | |
Microarchitecture | Nehalem |
Platform | Calpella |
Chipset | Ibex Peak |
Core Name | Clarksfield |
Core Family | 6 |
Core Model | 30 |
Core Stepping | B1 |
Process | 45 nm |
Transistors | 774,000,000 |
Technology | CMOS |
Die | 296 mm² |
Word Size | 64 bit |
Cores | 4 |
Threads | 8 |
Max Memory | 8 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 55 W |
OP Temperature | 0 °C – 100 °C |
The Core i7-940XM Extreme Edition is a 64-bit quad-core microprocessor introduced by Intel in early 2010 for the mobile market. The Core i7-940XM EE, which operated at 2.13 GHz with turbo frequency of up to 3.33 GHz for a single core was Intel's flagship mobile processor for the Nehalem microarchitecture. The 940XM is identical to the i7-920XM aside from a slightly higer base/Turbo clock speed. The chip is manufactured in 45 nm process. The i7-940XM supports 8GB of memory and has a thermal design power of 55 W.
Cache[edit]
- Main article: Nehalem § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Graphics[edit]
This MPU has no integrated graphics processing unit.
Expansions[edit]
Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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See also[edit]
Facts about "Core i7-940XM Extreme Edition - Intel"
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |