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{{amd title|Athlon MP 2000+}}
 
{{amd title|Athlon MP 2000+}}
−
{{mpu
+
{{chip
 
| name                = AMD Athlon MP 2000+
 
| name                = AMD Athlon MP 2000+
 
| no image            = yes
 
| no image            = yes
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| max memory          = 4 GiB
 
| max memory          = 4 GiB
  
−
| electrical          = Yes
+
 
 
| v core              = 1.65 V
 
| v core              = 1.65 V
 
| v core tolerance    =  
 
| v core tolerance    =  
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| tstorage max        = 100 °C
 
| tstorage max        = 100 °C
  
−
| packaging          = Yes
+
|package module 1={{packages/amd/pga-453}}
−
| package 0          = OPGA-453
 
−
| package 0 type      = OPGA
 
−
| package 0 pins      = 453
 
−
| package 0 pitch    = 1.27 mm
 
−
| package 0 width    = 49.53 mm
 
−
| package 0 length    = 49.53 mm
 
−
| package 0 height    = 1.942
 
−
| socket 0            = Socket A
 
−
| socket 0 type      = PGA-462
 
 
}}
 
}}
 
The '''Athlon MP 2000+''' (OPN ''AMSN2000DKT3C'') based on the {{amd|Thoroughbred|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in late [[2002]] for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12.5 multiplier), was manufactured on a newer [[130 nm]] copper processor technology in Fab 30 in Dresden, Germany.
 
The '''Athlon MP 2000+''' (OPN ''AMSN2000DKT3C'') based on the {{amd|Thoroughbred|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in late [[2002]] for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12.5 multiplier), was manufactured on a newer [[130 nm]] copper processor technology in Fab 30 in Dresden, Germany.
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== Cache ==
 
== Cache ==
 
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
 
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
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{{cache info
+
{{cache size
 +
|l1 cache=128 KiB
 
|l1i cache=64 KiB
 
|l1i cache=64 KiB
 
|l1i break=1x64 KiB
 
|l1i break=1x64 KiB
 
|l1i desc=2-way set associative
 
|l1i desc=2-way set associative
−
|l1i extra=
+
|l1i policy=
 
|l1d cache=64 KiB
 
|l1d cache=64 KiB
 
|l1d break=1x64 KiB
 
|l1d break=1x64 KiB
 
|l1d desc=2-way set associative
 
|l1d desc=2-way set associative
−
|l1d extra=
+
|l1d policy=
 
|l2 cache=256 KiB
 
|l2 cache=256 KiB
 
|l2 break=1x256 KiB
 
|l2 break=1x256 KiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
−
|l2 extra=
+
|l2 policy=
−
|l3 cache=
 
−
|l3 break=
 
−
|l3 desc=
 
−
|l3 extra=
 
 
}}
 
}}
  
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|avx=No
 
|avx=No
 
|avx2=No
 
|avx2=No
−
|avx512=No
+
 
 
|abm=No
 
|abm=No
 
|tbm=No
 
|tbm=No

Latest revision as of 14:20, 13 December 2017

Edit Values
AMD Athlon MP 2000+
General Info
DesignerAMD
ManufacturerAMD
Model NumberAthlon MP 2000+
Part NumberAMSN2000DKT3C
MarketServer
IntroductionAugust 27, 2002 (announced)
August 27, 2002 (launched)
Release Price$
ShopAmazon
General Specs
FamilyAthlon MP
LockedYes
Frequency1,667 MHz
Bus typeFSB
Bus speed133 MHz
Bus rate266 MT/s
Clock multiplier12.5
CPUID680, 681
Microarchitecture
MicroarchitectureK7
PlatformAthlon MP
ChipsetAMD-760MP
Core NameThoroughbred
Core Family6
Core Model8
Core Stepping0, 1
Process130 nm
Transistors37,200,000
TechnologyCMOS
Die85 mm²
Word Size32 bit
Cores1
Threads1
Max Memory4 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
Vcore1.65 V
Tjunction0 °C – 90 °C
Tcase0 °C – 90 °C
Tstorage-40 °C – 100 °C
Packaging
PackageOPGA-453 (PGA)
Dimension49.53 mm x 49.53 mm x 1.942 mm
Pitch1.27 mm
Pins453
InterconnectSocket A (PGA-462)

The Athlon MP 2000+ (OPN AMSN2000DKT3C) based on the Thoroughbred core was a 32-bit x86 multiprocessor developed by AMD and introduced in late 2002 for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12.5 multiplier), was manufactured on a newer 130 nm copper processor technology in Fab 30 in Dresden, Germany.

Cache[edit]

Main article: K7 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
1x64 KiB2-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
1x64 KiB2-way set associative 
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB16-way set associative 

Graphics[edit]

This MPU has no integrated graphics processing unit.

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
3DNow!3DNow! Extension
E3DNow!Extended 3DNow! Extension
SSEStreaming SIMD Extensions
x86-1616-bit x86
x86-3232-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
SmartMPSmartMP Technology
  • Advanced Configuration and Power Interface
    • Halt State
    • Stop Grant State

Documents[edit]

Datasheets[edit]

Others[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/athlon_mp/amsn2000dkt3c&oldid=69447"
Facts about "Athlon MP 2000+ - AMD"
RDF feed
has amd smartmp technologytrue +
has featureSmartMP Technology +, ACPI +, Halt State + and Stop Grant State +
has multiprocessing supporttrue +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +