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Difference between revisions of "amd/athlon mp/amp1900dms3c"
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{{amd title|Athlon MP 1900+}}
 
{{amd title|Athlon MP 1900+}}
−
{{mpu
+
{{chip
 
| name                = AMD Athlon MP 1900+
 
| name                = AMD Athlon MP 1900+
 
| no image            = yes
 
| no image            = yes
Line 46: Line 46:
 
| max memory          = 4 GiB
 
| max memory          = 4 GiB
  
−
| electrical          = Yes
+
 
 
| v core              = 1.75 V
 
| v core              = 1.75 V
 
| v core tolerance    =  
 
| v core tolerance    =  
Line 61: Line 61:
 
| tstorage max        = 100 °C
 
| tstorage max        = 100 °C
  
−
| packaging          = Yes
+
|package module 1={{packages/amd/pga-453}}
−
| package 0          = OPGA-453
 
−
| package 0 type      = OPGA
 
−
| package 0 pins      = 453
 
−
| package 0 pitch    = 1.27 mm
 
−
| package 0 width    = 49.53 mm
 
−
| package 0 length    = 49.53 mm
 
−
| package 0 height    = 1.942
 
−
| socket 0            = Socket A
 
−
| socket 0 type      = PGA-462
 
 
}}
 
}}
 
The '''Athlon MP 1900+''' (OPN ''AMP1900DMS3C'') based on the {{amd|Palomino|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in late [[2001]] for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12 multiplier). This processor, which was based on the {{amd|K7|K7 microarchitecture|l=arch}}, was manufactured on a mature [[180 nm]] copper interconnect technology at AMD's Fab 30 in Dresden, Germany.
 
The '''Athlon MP 1900+''' (OPN ''AMP1900DMS3C'') based on the {{amd|Palomino|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in late [[2001]] for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12 multiplier). This processor, which was based on the {{amd|K7|K7 microarchitecture|l=arch}}, was manufactured on a mature [[180 nm]] copper interconnect technology at AMD's Fab 30 in Dresden, Germany.
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== Cache ==
 
== Cache ==
 
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
 
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
−
{{cache info
+
{{cache size
 +
|l1 cache=128 KiB
 
|l1i cache=64 KiB
 
|l1i cache=64 KiB
 
|l1i break=1x64 KiB
 
|l1i break=1x64 KiB
 
|l1i desc=2-way set associative
 
|l1i desc=2-way set associative
−
|l1i extra=
+
|l1i policy=
 
|l1d cache=64 KiB
 
|l1d cache=64 KiB
 
|l1d break=1x64 KiB
 
|l1d break=1x64 KiB
 
|l1d desc=2-way set associative
 
|l1d desc=2-way set associative
−
|l1d extra=
+
|l1d policy=
 
|l2 cache=256 KiB
 
|l2 cache=256 KiB
 
|l2 break=1x256 KiB
 
|l2 break=1x256 KiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
−
|l2 extra=
+
|l2 policy=
−
|l3 cache=
 
−
|l3 break=
 
−
|l3 desc=
 
−
|l3 extra=
 
 
}}
 
}}
  
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== Features ==  
 
== Features ==  
−
{{mpu features
+
{{x86 features
−
| mmx         = Yes
+
|real=No
−
| emmx       = Yes
+
|protected=No
−
| 3dnow       = Yes
+
|smm=No
−
| e3dnow     = Yes
+
|fpu=No
−
| sse        = Yes
+
|x8616=No
−
| amd smartmp = Yes
+
|x8632=No
 +
|x8664=No
 +
|nx=No
 +
|mmx=No
 +
|emmx=No
 +
|sse=Yes
 +
|sse2=No
 +
|sse3=No
 +
|ssse3=No
 +
|sse41=No
 +
|sse42=No
 +
|sse4a=No
 +
|sse_gfni=No
 +
|avx=No
 +
|avx_gfni=No
 +
|avx2=No
 +
|avx512f=No
 +
|avx512cd=No
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=No
 +
|avx512dq=No
 +
|avx512vl=No
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx512vnni=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|avx512gfni=No
 +
|avx512vaes=No
 +
|avx512vbmi2=No
 +
|avx512bitalg=No
 +
|avx512vpclmulqdq=No
 +
|abm=No
 +
|tbm=No
 +
|bmi1=No
 +
|bmi2=No
 +
|fma3=No
 +
|fma4=No
 +
|aes=No
 +
|rdrand=No
 +
|sha=No
 +
|xop=No
 +
|adx=No
 +
|clmul=No
 +
|f16c=No
 +
|bfloat16=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|tvb=No
 +
|bpt=No
 +
|eist=No
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|tme=No
 +
|mktme=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=No
 +
|vpro=No
 +
|vtx=No
 +
|vtd=No
 +
|ept=No
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|dlboost=No
 +
|3dnow=Yes
 +
|e3dnow=Yes
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=Yes
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 
}}
 
}}
 
* Advanced Configuration and Power Interface [[has feature::ACPI| ]]
 
* Advanced Configuration and Power Interface [[has feature::ACPI| ]]

Latest revision as of 21:49, 3 September 2024

Edit Values
AMD Athlon MP 1900+
General Info
DesignerAMD
ManufacturerAMD
Model NumberAthlon MP 1900+
Part NumberAMP1900DMS3C
MarketServer
IntroductionDecember 12, 2001 (announced)
December 12, 2001 (launched)
Release Price$319
ShopAmazon
General Specs
FamilyAthlon MP
LockedYes
Frequency1,600 MHz
Bus typeFSB
Bus speed133 MHz
Bus rate266 MT/s
Clock multiplier12
CPUID662
Microarchitecture
MicroarchitectureK7
PlatformAthlon MP
ChipsetAMD-760MP
Core NamePalomino
Core Family6
Core Model6
Core Stepping2
Process180 nm
Transistors37,500,000
TechnologyCMOS
Die128 mm²
Word Size32 bit
Cores1
Threads1
Max Memory4 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
Vcore1.75 V
TDP66 W
TDP (Typical)58.9 W
Tjunction0 °C – 95 °C
Tcase0 °C – 95 °C
Tstorage-40 °C – 100 °C
Packaging
PackageOPGA-453 (PGA)
Dimension49.53 mm x 49.53 mm x 1.942 mm
Pitch1.27 mm
Pins453
InterconnectSocket A (PGA-462)

The Athlon MP 1900+ (OPN AMP1900DMS3C) based on the Palomino core was a 32-bit x86 multiprocessor developed by AMD and introduced in late 2001 for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12 multiplier). This processor, which was based on the K7 microarchitecture, was manufactured on a mature 180 nm copper interconnect technology at AMD's Fab 30 in Dresden, Germany.

Cache[edit]

Main article: K7 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
1x64 KiB2-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
1x64 KiB2-way set associative 
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB16-way set associative 

Graphics[edit]

This MPU has no integrated graphics processing unit.

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
3DNow!3DNow! Extension
E3DNow!Extended 3DNow! Extension
SSEStreaming SIMD Extensions
AMD-VAMD Virtualization
  • Advanced Configuration and Power Interface
    • Halt State
    • Stop Grant State

Documents[edit]

Datasheets[edit]

Others[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/athlon_mp/amp1900dms3c&oldid=102508"
Facts about "Athlon MP 1900+ - AMD"
RDF feed
has amd smartmp technologytrue +
has featureSmartMP Technology +, ACPI +, Halt State + and Stop Grant State +
has multiprocessing supporttrue +
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +