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Difference between revisions of "amd/athlon mp/amsn2000dut3c"
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{{amd title|Athlon MP 2000+}} | {{amd title|Athlon MP 2000+}} | ||
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| name = AMD Athlon MP 2000+ | | name = AMD Athlon MP 2000+ | ||
| no image = yes | | no image = yes | ||
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| max memory = 4 GiB | | max memory = 4 GiB | ||
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| v core = 1.6 V | | v core = 1.6 V | ||
| v core tolerance = | | v core tolerance = | ||
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| tstorage max = 100 °C | | tstorage max = 100 °C | ||
− | + | |package module 1={{packages/amd/pga-453}} | |
− | | package | ||
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}} | }} | ||
− | The '''Athlon MP 2000+''' (OPN ''AMSN2000DUT3C'') based on the {{amd|Thoroughbred|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in late [[2002]] for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12.5 multiplier), was manufactured on a newer [[130 nm | + | The '''Athlon MP 2000+''' (OPN ''AMSN2000DUT3C'') based on the {{amd|Thoroughbred|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in late [[2002]] for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12.5 multiplier), was manufactured on a newer [[130 nm]] copper processor technology in Fab 30 in Dresden, Germany. |
== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}} | {{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}} | ||
− | {{cache | + | {{cache size |
+ | |l1 cache=128 KiB | ||
|l1i cache=64 KiB | |l1i cache=64 KiB | ||
|l1i break=1x64 KiB | |l1i break=1x64 KiB | ||
|l1i desc=2-way set associative | |l1i desc=2-way set associative | ||
− | |l1i | + | |l1i policy= |
|l1d cache=64 KiB | |l1d cache=64 KiB | ||
|l1d break=1x64 KiB | |l1d break=1x64 KiB | ||
|l1d desc=2-way set associative | |l1d desc=2-way set associative | ||
− | |l1d | + | |l1d policy= |
|l2 cache=256 KiB | |l2 cache=256 KiB | ||
|l2 break=1x256 KiB | |l2 break=1x256 KiB | ||
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
− | |l2 | + | |l2 policy= |
− | | | + | }} |
− | | | + | |
− | | | + | == Graphics == |
− | | | + | This MPU has no integrated graphics processing unit. |
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=No | ||
+ | |nx=No | ||
+ | |3dnow=Yes | ||
+ | |e3dnow=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=No | ||
+ | |sse3=No | ||
+ | |ssse3=No | ||
+ | |sse41=No | ||
+ | |sse42=No | ||
+ | |sse4a=No | ||
+ | |avx=No | ||
+ | |avx2=No | ||
+ | |||
+ | |abm=No | ||
+ | |tbm=No | ||
+ | |bmi1=No | ||
+ | |bmi2=No | ||
+ | |fma3=No | ||
+ | |fma4=No | ||
+ | |aes=No | ||
+ | |rdrand=No | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=No | ||
+ | |clmul=No | ||
+ | |f16c=No | ||
+ | |tbt1=No | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=No | ||
+ | |flex=No | ||
+ | |isrt=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=No | ||
+ | |txt=No | ||
+ | |ht=No | ||
+ | |vpro=No | ||
+ | |vtx=No | ||
+ | |vtd=No | ||
+ | |ept=No | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |smartmp=Yes | ||
+ | |powernow=No | ||
+ | |amdv=No | ||
+ | |rvi=No | ||
}} | }} | ||
+ | * Advanced Configuration and Power Interface [[has feature::ACPI| ]] | ||
+ | ** [[has feature::Halt State]] | ||
+ | ** [[has feature::Stop Grant State]] | ||
+ | |||
+ | == Documents == | ||
+ | === Datasheets === | ||
+ | * [[:File:AMD Athlon MP Processor Model 8 Data Sheet for Multiprocessor Platforms.pdf|AMD Athlon MP Processor Model 8 Data Sheet for Multiprocessor Platforms]]; Publication # 25722 Rev. E; Issue Date: March 2003. | ||
+ | === Others === | ||
+ | * [[:File:System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors.pdf|System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors]]; Publication # 25325; Rev: B; August 2002. |
Latest revision as of 15:20, 13 December 2017
Edit Values | |||||||||||
AMD Athlon MP 2000+ | |||||||||||
General Info | |||||||||||
Designer | AMD | ||||||||||
Manufacturer | AMD | ||||||||||
Model Number | Athlon MP 2000+ | ||||||||||
Part Number | AMSN2000DUT3C | ||||||||||
Market | Server | ||||||||||
Introduction | August 27, 2002 (announced) August 27, 2002 (launched) | ||||||||||
Shop | Amazon | ||||||||||
General Specs | |||||||||||
Family | Athlon MP | ||||||||||
Locked | Yes | ||||||||||
Frequency | 1,667 MHz | ||||||||||
Bus type | FSB | ||||||||||
Bus speed | 133 MHz | ||||||||||
Bus rate | 266 MT/s | ||||||||||
Clock multiplier | 12.5 | ||||||||||
CPUID | 680, 681 | ||||||||||
Microarchitecture | |||||||||||
Microarchitecture | K7 | ||||||||||
Platform | Athlon MP | ||||||||||
Chipset | AMD-760MP | ||||||||||
Core Name | Thoroughbred | ||||||||||
Core Family | 6 | ||||||||||
Core Model | 8 | ||||||||||
Core Stepping | 0, 1 | ||||||||||
Process | 130 nm | ||||||||||
Transistors | 37,200,000 | ||||||||||
Technology | CMOS | ||||||||||
Die | 85 mm² | ||||||||||
Word Size | 32 bit | ||||||||||
Cores | 1 | ||||||||||
Threads | 1 | ||||||||||
Max Memory | 4 GiB | ||||||||||
Multiprocessing | |||||||||||
Max SMP | 2-Way (Multiprocessor) | ||||||||||
Electrical | |||||||||||
Vcore | 1.6 V | ||||||||||
TDP | 58.2 W | ||||||||||
TDP (Typical) | 52.8 W | ||||||||||
Tjunction | 0 °C – 90 °C | ||||||||||
Tcase | 0 °C – 90 °C | ||||||||||
Tstorage | -40 °C – 100 °C | ||||||||||
Packaging | |||||||||||
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The Athlon MP 2000+ (OPN AMSN2000DUT3C) based on the Thoroughbred core was a 32-bit x86 multiprocessor developed by AMD and introduced in late 2002 for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12.5 multiplier), was manufactured on a newer 130 nm copper processor technology in Fab 30 in Dresden, Germany.
Cache[edit]
- Main article: K7 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics[edit]
This MPU has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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- Advanced Configuration and Power Interface
- Halt State
- Stop Grant State
Documents[edit]
Datasheets[edit]
- AMD Athlon MP Processor Model 8 Data Sheet for Multiprocessor Platforms; Publication # 25722 Rev. E; Issue Date: March 2003.
Others[edit]
- System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors; Publication # 25325; Rev: B; August 2002.
Facts about "Athlon MP 2000+ - AMD"
has feature | ACPI +, Halt State + and Stop Grant State + |
l1d$ description | 2-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |