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Difference between revisions of "amd/athlon mp/ahx1000ams3c"
< amd‎ | athlon mp

m (Bot: switching template from {{mpu}} to a more generic {{chip}})
 
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{{amd title|Athlon MP 1000}}
 
{{amd title|Athlon MP 1000}}
−
{{mpu
+
{{chip
 
| name                = AMD Athlon MP 1000
 
| name                = AMD Athlon MP 1000
 
| no image            = yes
 
| no image            = yes
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| max memory          = 4 GiB
 
| max memory          = 4 GiB
  
−
| electrical          = Yes
+
 
 
| v core              = 1.75 V
 
| v core              = 1.75 V
 
| v core tolerance    =  
 
| v core tolerance    =  
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== Cache ==
 
== Cache ==
 
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
 
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
−
{{cache info
+
{{cache size
 +
|l1 cache=128 KiB
 
|l1i cache=64 KiB
 
|l1i cache=64 KiB
 
|l1i break=1x64 KiB
 
|l1i break=1x64 KiB
 
|l1i desc=2-way set associative
 
|l1i desc=2-way set associative
−
|l1i extra=
+
|l1i policy=
 
|l1d cache=64 KiB
 
|l1d cache=64 KiB
 
|l1d break=1x64 KiB
 
|l1d break=1x64 KiB
 
|l1d desc=2-way set associative
 
|l1d desc=2-way set associative
−
|l1d extra=
+
|l1d policy=
 
|l2 cache=256 KiB
 
|l2 cache=256 KiB
 
|l2 break=1x256 KiB
 
|l2 break=1x256 KiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
−
|l2 extra=
+
|l2 policy=
−
|l3 cache=
 
−
|l3 break=
 
−
|l3 desc=
 
−
|l3 extra=
 
 
}}
 
}}
  
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== Features ==  
 
== Features ==  
−
{{mpu features
+
{{x86 features
−
| mmx        = Yes
+
|real=Yes
−
| emmx        = Yes
+
|protected=Yes
−
| 3dnow       = Yes
+
|smm=Yes
−
| e3dnow     = Yes
+
|fpu=Yes
−
| sse         = Yes
+
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=No
 +
|nx=No
 +
|3dnow=Yes
 +
|e3dnow=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=No
 +
|sse3=No
 +
|ssse3=No
 +
|sse41=No
 +
|sse42=No
 +
|sse4a=No
 +
|avx=No
 +
|avx2=No
 +
 
 +
|abm=No
 +
|tbm=No
 +
|bmi1=No
 +
|bmi2=No
 +
|fma3=No
 +
|fma4=No
 +
|aes=No
 +
|rdrand=No
 +
|sha=No
 +
|xop=No
 +
|adx=No
 +
|clmul=No
 +
|f16c=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=No
 +
|flex=No
 +
|isrt=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=No
 +
|vpro=No
 +
|vtx=No
 +
|vtd=No
 +
|ept=No
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|smartmp=Yes
 +
|powernow=No
 +
|amdv=No
 +
|rvi=No
 
}}
 
}}
 
* Advanced Configuration and Power Interface [[has feature::ACPI| ]]
 
* Advanced Configuration and Power Interface [[has feature::ACPI| ]]

Latest revision as of 15:20, 13 December 2017

Edit Values
AMD Athlon MP 1000
General Info
DesignerAMD
ManufacturerAMD
Model NumberAthlon MP 1000
Part NumberAHX1000AMS3C
MarketServer
IntroductionJune 5, 2001 (announced)
June 5, 2001 (launched)
Release Price$215
ShopAmazon
General Specs
FamilyAthlon MP
LockedYes
Frequency1000 MHz
Bus typeFSB
Bus speed133 MHz
Bus rate266 MT/s
Clock multiplier7.5
CPUID662
Microarchitecture
MicroarchitectureK7
PlatformAthlon MP
ChipsetAMD-760MP
Core NamePalomino
Core Family6
Core Model6
Core Stepping2
Process180 nm
Transistors37,500,000
TechnologyCMOS
Die128 mm²
Word Size32 bit
Cores1
Threads1
Max Memory4 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
Vcore1.75 V
TDP46.1 W
TDP (Typical)41.3 W
Tjunction0 °C – 95 °C
Tcase0 °C – 95 °C
Tstorage-40 °C – 100 °C

Athlon MP 1000 (OPN AHX1000AMS3C) based on the Palomino core was a 32-bit x86 multiprocessor developed by AMD and introduced in 2001 for the server and workstation market. The MP 1000 was AMD's first dual-socket microprocessor (along with the 1200). This model operated at 1 GHz with a FSB transfer rate of 266 MT/s with a typical TDP of 41.3 W. This processor, which was based on the K7 microarchitecture, was manufactured on a mature 180 nm copper interconnect technology at AMD's Fab 30 in Dresden, Germany.

Cache[edit]

Main article: K7 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
1x64 KiB2-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
1x64 KiB2-way set associative 
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB16-way set associative 

Graphics[edit]

This MPU has no integrated graphics processing unit.

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
3DNow!3DNow! Extension
E3DNow!Extended 3DNow! Extension
SSEStreaming SIMD Extensions
x86-1616-bit x86
x86-3232-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
SmartMPSmartMP Technology
  • Advanced Configuration and Power Interface
    • Halt State
    • Stop Grant State

Documents[edit]

Datasheets[edit]

Others[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/athlon_mp/ahx1000ams3c&oldid=69437"
Facts about "Athlon MP 1000 - AMD"
RDF feed
has featureACPI +, Halt State + and Stop Grant State +
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +