From WikiChip
Difference between revisions of "intel/xeon e5/e5-2603 v4"
< intel‎ | xeon e5

m (Bot: moving all {{mpu}} to {{chip}})
 
(10 intermediate revisions by 2 users not shown)
Line 1: Line 1:
 
{{intel title|Xeon E5-2603 v4}}
 
{{intel title|Xeon E5-2603 v4}}
−
{{mpu
+
{{chip
 
| name                = Xeon E5-2603 v4
 
| name                = Xeon E5-2603 v4
 
| no image            = Yes
 
| no image            = Yes
Line 10: Line 10:
 
| model number        = E5-2603 v4
 
| model number        = E5-2603 v4
 
| part number        = CM8066002032805
 
| part number        = CM8066002032805
−
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Server
 
| market              = Server
 
| first announced    = June 20, 2016
 
| first announced    = June 20, 2016
Line 31: Line 31:
 
| s-spec              = SR2P0
 
| s-spec              = SR2P0
 
| s-spec es          =  
 
| s-spec es          =  
−
| s-spec qs          =  
+
| s-spec qs          = QKEV
 
| cpuid              = 406F1
 
| cpuid              = 406F1
  
Line 51: Line 51:
 
| max memory          = 1,536 GiB
 
| max memory          = 1,536 GiB
  
−
| electrical          = Yes
+
 
 
| v core              = 1.82 V
 
| v core              = 1.82 V
 
| v core tolerance    =  
 
| v core tolerance    =  
Line 80: Line 80:
 
| socket 0 type      = LGA
 
| socket 0 type      = LGA
 
}}
 
}}
−
The '''Xeon E5-2603 v4''' is a {{arch|64}} [[hexa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for basic 2S environments (1U square form factor). Operating at 1.7 GHz with a {{intel|turbo boost}} frequency of 3.2 GHz for a single active core, this MPU has a TDP of 85 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
+
The '''Xeon E5-2603 v4''' is a {{arch|64}} [[hexa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for basic 2S environments (1U square form factor). Operating at 1.7 GHz with no {{intel|turbo boost}} support, this MPU has a TDP of 85 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}). This specific model has no hyper-threading support.
 +
 
 +
== Cache ==
 +
{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
 +
{{cache info
 +
|l1i cache=192 KiB
 +
|l1i break=6x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1i extra=(per core, write-back)
 +
|l1d cache=192 KiB
 +
|l1d break=6x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d extra=(per core, write-back)
 +
|l2 cache=1.5 MiB
 +
|l2 break=6x256 KiB
 +
|l2 desc=8-way set associative
 +
|l2 extra=(per core, write-back)
 +
|l3 cache=15 MiB
 +
|l3 break=6x2.5 MiB
 +
|l3 desc=20-way set associative
 +
|l3 extra=(shared, per core, write-back)
 +
}}
 +
 
 +
== Graphics ==
 +
This microprocessor has no [[integrated graphics processing unit]].
 +
 
 +
== Memory controller ==
 +
{{integrated memory controller
 +
| type              = DDR4-1866
 +
| controllers        = 1
 +
| channels          = 4
 +
| ecc support        = Yes
 +
| max bandwidth      = 55.63 GiB/s
 +
| bandwidth schan    = 13.91 GiB/s
 +
| bandwidth dchan    = 27.82 GiB/s
 +
| max memory        = 1,536 GiB
 +
| pae                = 46 bit
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 40
 +
| pcie config        = x4
 +
| pcie config 1      = x8
 +
| pcie config 2      = x16
 +
}}
 +
 
 +
== Features ==
 +
{{x86 features
 +
| em64t      = Yes
 +
| nx          = Yes
 +
| txt        = Yes
 +
| tsx        = Yes
 +
| vpro        = Yes
 +
| ht          =
 +
| tbt1        =
 +
| tbt2        =
 +
| tbmt3      =
 +
| bpt        =
 +
| vt-x        = Yes
 +
| vt-d        = Yes
 +
| ept        = Yes
 +
| mmx        = Yes
 +
| sse        = Yes
 +
| sse2        = Yes
 +
| sse3        = Yes
 +
| ssse3      = Yes
 +
| sse4.1      = Yes
 +
| sse4.2      = Yes
 +
| aes        = Yes
 +
| pclmul      = Yes
 +
| avx        = Yes
 +
| avx2        = Yes
 +
| bmi        = Yes
 +
| bmi1        = Yes
 +
| bmi2        = Yes
 +
| f16c        = Yes
 +
| fma3        = Yes
 +
| mpx        =
 +
| sgx        =
 +
| eist        = Yes
 +
| secure key  = Yes
 +
| os guard    = Yes
 +
| intel at    =
 +
| intel ipt  =
 +
}}

Latest revision as of 15:27, 13 December 2017

Edit Values
Xeon E5-2603 v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-2603 v4
Part NumberCM8066002032805
S-SpecSR2P0
QKEV (QS)
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
Release Price$213.00
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-2000
LockedYes
Frequency1,700 MHz
Bus typeQPI
Bus speed3,200 MHz
Bus rate2 × 6.4 GT/s
Clock multiplier17
CPUID406F1
Microarchitecture
MicroarchitectureBroadwell
PlatformGrantley EP 2S
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingR0
Process14 nm
Transistors3,200,000,000
TechnologyCMOS
Die246.24 mm²
Word Size64 bit
Cores6
Threads6
Max Memory1,536 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP85 W
Tcase0 °C – 73 °C
Tstorage-25 °C – 125 °C

The Xeon E5-2603 v4 is a 64-bit hexa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for basic 2S environments (1U square form factor). Operating at 1.7 GHz with no turbo boost support, this MPU has a TDP of 85 W and is manufactured on a 14 nm process (based on Broadwell). This specific model has no hyper-threading support.

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 192 KiB
196,608 B
0.188 MiB
6x32 KiB 8-way set associative (per core, write-back)
L1D$ 192 KiB
196,608 B
0.188 MiB
6x32 KiB 8-way set associative (per core, write-back)
L2$ 1.5 MiB
1,536 KiB
1,572,864 B
0.00146 GiB
6x256 KiB 8-way set associative (per core, write-back)
L3$ 15 MiB
15,360 KiB
15,728,640 B
0.0146 GiB
6x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-1866
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 55.63 GiB/s
Bandwidth (single) 13.91 GiB/s
Bandwidth (dual) 27.82 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2603_v4&oldid=70978"
Facts about "Xeon E5-2603 v4 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E5-2603 v4 - Intel#io +
base frequency1,700 MHz (1.7 GHz, 1,700,000 kHz) +
bus links2 +
bus rate6,400 MT/s (6.4 GT/s, 6,400,000 kT/s) +
bus speed3,200 MHz (3.2 GHz, 3,200,000 kHz) +
bus typeQPI +
chipsetC610 Series +
clock multiplier17 +
core count6 +
core family6 +
core model4F +
core nameBroadwell EP +
core steppingR0 +
core voltage1.82 V (18.2 dV, 182 cV, 1,820 mV) +
cpuid406F1 +
designerIntel +
die area246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) +
familyXeon E5 +
first announcedJune 20, 2016 +
first launchedJune 20, 2016 +
full page nameintel/xeon e5/e5-2603 v4 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel vpro technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
io voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
io voltage tolerance3% +
l1d$ description8-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description8-way set associative +
l1i$ size192 KiB (196,608 B, 0.188 MiB) +
l2$ description8-way set associative +
l2$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l3$ description20-way set associative +
l3$ size15 MiB (15,360 KiB, 15,728,640 B, 0.0146 GiB) +
ldateJune 20, 2016 +
manufacturerIntel +
market segmentServer +
max case temperature346.15 K (73 °C, 163.4 °F, 623.07 °R) +
max cpu count2 +
max memory1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) +
max pcie lanes40 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureBroadwell +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model numberE5-2603 v4 +
nameXeon E5-2603 v4 +
part numberCM8066002032805 +
platformGrantley EP 2S +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 213.00 (€ 191.70, £ 172.53, ¥ 22,009.29) +
s-specSR2P0 +
s-spec (qs)QKEV +
seriesE5-2000 +
smp max ways2 +
tdp85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technologyCMOS +
thread count6 +
transistor count3,200,000,000 +
word size64 bit (8 octets, 16 nibbles) +