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Difference between revisions of "pezy/pezy-scx/pezy-scnp"
< pezy‎ | pezy-scx

(Created page with "{{pezy title|PEZY-SCnp}} {{mpu | name = PEZY-SCnp | no image = | image = | image size = | caption = | designer...")
 
 
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{{pezy title|PEZY-SCnp}}
 
{{pezy title|PEZY-SCnp}}
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{{mpu
+
{{chip
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| name               = PEZY-SCnp
+
|name=PEZY-SCnp
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| no image           =
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|image=pezy-scnp (front).png
−
| image              =
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|designer=PEZY
−
| image size          =
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|manufacturer=TSMC
−
| caption            =  
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|model number=PEZY-SCnp
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| designer           = PEZY
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|market=Supercomputer
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| manufacturer       = TSMC
+
|first announced=May 6, 2016
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| model number       = PEZY-SCnp
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|first launched=May 6, 2016
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| part number        =
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|family=PEZY-SCx
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| market             = Industrial
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|frequency=766.66 MHz
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| first announced     = May 6, 2016
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|process=28 nm
−
| first launched     = May 6, 2016
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|technology=CMOS
−
| last order         =  
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|core count=1,024
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| last shipment      =  
+
|thread count=8,192
 +
|power=100 W
 +
|average power=70 W
 +
|v core=0.95 V
 +
|package module 1={{packages/pezy/fcbga-2397}}
 +
|electrical=Yes
 +
|packaging=Yes
 +
|package 0=fcBGA-2397
 +
|package 0 type=fcBGA
 +
|package 0 pins=2,397
 +
|package 0 pitch=1 mm
 +
|package 0 width=50 mm
 +
|package 0 length=50 mm
 +
|socket 0=BGA-2397
 +
|socket 0 type=BGA
 +
}}
 +
'''PEZY-SCnp''' (SC - '''Super Computer'''; np - '''New Package''') is a revised version of the {{pezy|PEZY-SC}} model by [[PEZY]] introduced in may of 2016. The new chip, which made use of a slightly different package in order to address a number of signal-related issues (DRAM/PCIe signal failures). The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. Operating at 766 MHz, the processor has a peak performance of 3.14 [[TFLOPS]] (single-precision) and 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. As with the PEZY-SC, the SCnp is also manufactured on [[28 nm process|TSMC's 28HPC+]].
 +
{{#set:
 +
| peak flops (single-precision) = {{#expr:766666666 * 4 * 1024}} FLOPS
 +
| peak flops (double-precision) = {{#expr:766666666 * 2 * 1024}} FLOPS
 +
}}
 +
 
 +
== Architecture ==
 +
{{further|pezy/pezy-scx/pezy-sc#Architecture|pezy/pezy-scx#Architecture|l1=PEZY-SC § Architecture|l2=PEZY-SCx § Architecture}}
 +
The PEZY-SCnp's architecture is identical to the {{pezy|PEZY-SC}}.
 +
 
 +
== Cache ==
 +
PEZY-SC's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared).
 +
{{cache size
 +
|l1 cache=64 KiB
 +
|l1i cache=32 KiB
 +
|l1i break=2x16 KiB
 +
|l1d cache=32 KiB
 +
|l1d break=2x16 KiB
 +
|l2 cache=64 KiB
 +
|l2 break=1x64 KiB
 +
}}
  
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| family              =  
+
The chip integrates a multi-level cache hierarchy:
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| series              =  
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{{cache size
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| locked              =  
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|l1 cache=3 MiB
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| frequency          = 766.66 MHz
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|l1i cache=2 MiB
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| bus type            =  
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|l1i break=1024x2 KiB
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| bus speed          = 66.66 MHz
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|l1i desc=per processor element
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| bus rate            =  
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|l1d cache=1 MiB
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| clock multiplier    = 11.5
+
|l1d break=512x2 KiB
 +
|l1d desc=per 2 processor elements
 +
|l1d policy=
 +
|l2 cache=4 MiB
 +
|l2 break=4x2 MiB
 +
|l2 desc=per city
 +
|l2 policy=write-back
 +
|l3 cache=8 MiB
 +
|l3 break=4x2 MiB
 +
|l3 desc=per prefecture
 +
|l3 policy=
 +
}}
  
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| microarch          =
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Additionally, there is another 16 MiB of scratch-pad memory consisting of 16 KiB per PE.
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| platform            =
 
−
| chipset            =
 
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| core name          =
 
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| core family        =
 
−
| core model          =
 
−
| core stepping      =
 
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| process            = 28 nm
 
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| transistors        =
 
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| technology          = CMOS
 
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| die area            = 411.6 mm²
 
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| die width          = 21.1 mm
 
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| die length          = 19.5 mm
 
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| word size          =
 
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| core count          = 1024
 
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| thread count        =
 
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| max cpus            =
 
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| max memory          =
 
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| max memory addr    =
 
  
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| electrical          = Yes
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== Memory controller ==
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| power              = 70 W
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{{memory controller
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| v core              = 0.9 V
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|type=DDR4-2133
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| v core tolerance    =  
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|ecc=Yes
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| v io                =
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|controllers=8
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| v io tolerance      =  
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|channels=8
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| sdp                =  
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|width=64 bit
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| tdp                =  
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|max bandwidth=127.156 GiB/s
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| ctdp down          =  
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|bandwidth schan=15.89 GiB/s
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| ctdp down frequency =  
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|bandwidth dchan=31.79 GiB/s
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| ctdp up            =
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|bandwidth qchan=63.58 GiB/
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| ctdp up frequency  =
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|bandwidth hchan=95.37 GiB/s
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| temp min            =
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|bandwidth ochan=127.156 GiB/s
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| temp max           =  
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}}
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| tjunc min          = <!-- °C -->
 
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| tjunc max          =  
 
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| tcase min          =  
 
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| tcase max          =  
 
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| tstorage min        =  
 
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| tstorage max        =
 
  
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| packaging          = Yes
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== Expansions ==
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| package 0          = fcBGA-2397
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{{expansions main
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| package 0 type      = fcBGA
+
|
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| package 0 pins      = 2,397
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{{expansions entry
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| package 0 pitch    = 1 mm
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|type=PCIe
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| package 0 width    = 50 mm
+
|pcie revision=3.0
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| package 0 length    = 50 mm
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|pcie lanes=32
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| package 0 height    =  
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|pcie config=4x8
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| socket 0            = BGA-2397
+
}}
−
| socket 0 type      = BGA
 
 
}}
 
}}
−
'''PEZY-SCnp''' (SC - Super Computer; np - New Package) is a revised version of the {{pezy|PEZY-SC}} model by [[PEZY]] introduced in may of 2016. The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. The PEZY-SCnp is said to deliver 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. PEZY-SC was As with the PEZ-SC, the SCnp is also manufactured on TSMC's 28HPC+ ([[28 nm process]]).
 

Latest revision as of 10:15, 22 September 2018

Edit Values
PEZY-SCnp
pezy-scnp (front).png
General Info
DesignerPEZY
ManufacturerTSMC
Model NumberPEZY-SCnp
MarketSupercomputer
IntroductionMay 6, 2016 (announced)
May 6, 2016 (launched)
General Specs
FamilyPEZY-SCx
Frequency766.66 MHz
Microarchitecture
Process28 nm
TechnologyCMOS
Cores1,024
Threads8,192
Electrical
Power dissipation100 W
Power dissipation (average)70 W
Vcore0.95 V
Packaging
PackageFCBGA-2397 (BGA)pezy-scnp (back).png
Dimension50 mm x 50 mm
Pitch1 mm
Contacts2,397

PEZY-SCnp (SC - Super Computer; np - New Package) is a revised version of the PEZY-SC model by PEZY introduced in may of 2016. The new chip, which made use of a slightly different package in order to address a number of signal-related issues (DRAM/PCIe signal failures). The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. Operating at 766 MHz, the processor has a peak performance of 3.14 TFLOPS (single-precision) and 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. As with the PEZY-SC, the SCnp is also manufactured on TSMC's 28HPC+.


Architecture[edit]

Further information: PEZY-SC § Architecture and PEZY-SCx § Architecture

The PEZY-SCnp's architecture is identical to the PEZY-SC.

Cache[edit]

PEZY-SC's cache is separate from the ARM926's cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared).

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
65,536 B
0.0625 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
2x16 KiB  
L1D$32 KiB
32,768 B
0.0313 MiB
2x16 KiB  
L2$64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
  1x64 KiB  

The chip integrates a multi-level cache hierarchy:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$3 MiB
3,072 KiB
3,145,728 B
L1I$2 MiB
2,048 KiB
2,097,152 B
1024x2 KiBper processor element 
L1D$1 MiB
1,024 KiB
1,048,576 B
512x2 KiBper 2 processor elements 
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  4x2 MiBper citywrite-back
L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiBper prefecture 

Additionally, there is another 16 MiB of scratch-pad memory consisting of 16 KiB per PE.

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Controllers8
Channels8
Width64 bit
Max Bandwidth127.156 GiB/s
130,207.744 MiB/s
136.533 GB/s
136,532.715 MB/s
0.124 TiB/s
0.137 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s
Quad 63.58 GiB/
Hexa 95.37 GiB/s
Octa 127.156 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 32
Configuration: 4x8
Retrieved from "https://en.wikichip.org/w/index.php?title=pezy/pezy-scx/pezy-scnp&oldid=82698"
Facts about "PEZY-SCnp - PEZY"
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PEZY-SCnp - PEZY#package + and PEZY-SCnp - PEZY#pcie +
base frequency766.66 MHz (0.767 GHz, 766,660 kHz) +
core count1,024 +
core voltage0.95 V (9.5 dV, 95 cV, 950 mV) +
designerPEZY +
familyPEZY-SCx +
first announcedMay 6, 2016 +
first launchedMay 6, 2016 +
full page namepezy/pezy-scx/pezy-scnp +
has ecc memory supporttrue +
instance ofmicroprocessor +
l1$ size64 KiB (65,536 B, 0.0625 MiB) + and 3,072 KiB (3,145,728 B, 3 MiB) +
l1d$ descriptionper 2 processor elements +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) + and 1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ descriptionper processor element +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) + and 2,048 KiB (2,097,152 B, 2 MiB) +
l2$ descriptionper city +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + and 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ descriptionper prefecture +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldateMay 6, 2016 +
main imageFile:pezy-scnp (front).png +
manufacturerTSMC +
market segmentSupercomputer +
max memory bandwidth127.156 GiB/s (130,207.744 MiB/s, 136.533 GB/s, 136,532.715 MB/s, 0.124 TiB/s, 0.137 TB/s) +
max memory channels8 +
model numberPEZY-SCnp +
namePEZY-SCnp +
packageFCBGA-2397 +
peak flops (double-precision)1,570,133,331,968 FLOPS (1,570,133,331.968 KFLOPS, 1,570,133.332 MFLOPS, 1,570.133 GFLOPS, 1.57 TFLOPS, 0.00157 PFLOPS, 1.570133e-6 EFLOPS, 1.570133e-9 ZFLOPS) +
peak flops (single-precision)3,140,266,663,936 FLOPS (3,140,266,663.936 KFLOPS, 3,140,266.664 MFLOPS, 3,140.267 GFLOPS, 3.14 TFLOPS, 0.00314 PFLOPS, 3.140267e-6 EFLOPS, 3.140267e-9 ZFLOPS) +
power dissipation100 W (100,000 mW, 0.134 hp, 0.1 kW) +
power dissipation (average)70 W (70,000 mW, 0.0939 hp, 0.07 kW) +
process28 nm (0.028 μm, 2.8e-5 mm) +
supported memory typeDDR4-2133 +
technologyCMOS +
thread count8,192 +