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(Created page with "{{intrinsity title|FastMATH 3 GHz}} The '''FastMATH 3 GHz''' was a microprocessor developed by Intrinsity operating at 3 GHz. The processor incorporates a high-performance...")
 
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{{intrinsity title|FastMATH 3 GHz}}
 
{{intrinsity title|FastMATH 3 GHz}}
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{{chip
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| name                = FastMATH 3 GHz
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| no image            = Yes
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| image              =
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| image size          =
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| caption            =
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| designer            = Intrinsity
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| manufacturer        = TSMC
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| model number        = FastMATH-3
 +
| part number        =
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| part number 2      =
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| market              = Embedded
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| first announced    = 2003
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| first launched      =
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| last order          =
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| last shipment      =
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| family              = FastMATH
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| series              =
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| locked              =
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| frequency          = 3,000 MHz
 +
| bus type            = RapidIO
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| bus speed          = 500 MHz
 +
| bus rate            = 4 GT/s
 +
| clock multiplier    =
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| microarch          = FashMATH
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| platform            =
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| chipset            =
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| core name          =
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| core family        =
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| core model          =
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| core stepping      =
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| process            = 130 nm
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| transistors        =
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| technology          = Dynamic CMOS
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| die size            =
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| word size          = 32 bit
 +
| core count          = 1
 +
| thread count        = 1
 +
| max cpus            =
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| max memory          = 1 GiB
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| max memory addr    =
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 +
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| power              =
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| v core              = 1.25 V
 +
| v core tolerance    =
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| sdp                =
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| tdp                =
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| ctdp down          =
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| ctdp down frequency =
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| ctdp up            =
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| ctdp up frequency  =
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| temp min            =
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| temp max            =
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| tjunc min          =
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| tjunc max          =
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| tcase min          =
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| tcase max          =
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| tstorage min        =
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| tstorage max        =
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| packaging          = Yes
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| package 0          = CBGA-670
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| package 0 type      = CBGA
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| package 0 pins      = 670
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| package 0 pitch    =
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| package 0 width    =
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| package 0 length    =
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| package 0 height    =
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| socket 0            =
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| socket 0 type      =
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}}
 
The '''FastMATH 3 GHz''' was a microprocessor developed by [[Intrinsity]] operating at 3 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit.
 
The '''FastMATH 3 GHz''' was a microprocessor developed by [[Intrinsity]] operating at 3 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit.
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== Cache ==
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{{main|intrinsity/microarchitectures/fastmath#Memory_Hierarchy|l1=FastMATH § Cache}}
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{{cache info
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|l1i cache=16 KiB
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|l1i break=1x16 KiB
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|l1i desc=256 blocks × 16 words/block
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|l1d cache=16 KiB
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|l1d break=1x16 KiB
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|l1d desc=256 blocks × 16 words/block
 +
|l1d extra=write-through or write-back mode
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|l2 cache=1 MiB
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|l2 break=1x1 MiB
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|l2 desc=4-way set associative
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|l2 extra=(configurable as SRAM in 256 KiB increments)
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}}
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== Graphics ==
 +
This SoC has no integrated graphics processing unit.
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== Memory controller ==
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{{integrated memory controller
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| type              = DDR-400
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| controllers        = 1
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| channels          = 2
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| ecc support        =
 +
| max bandwidth      =
 +
| bandwidth schan    =
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| bandwidth dchan    =
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| max memory        = 1 GB
 +
}}
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== Matrix and Vector Unit ==
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* SIMD architecture
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* Operates on 4x4 array of {{arch|32}} elements
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* Fixed-point matrix, vector, and scalar data types
 +
 +
== Features ==
 +
* [[has feature::JTAG]] interface
 +
* 8-bit or 32-bit wide bus operates up to 66 MHz
 +
 +
{{DEFAULTSORT:FastMATH, 3}}

Latest revision as of 16:31, 13 December 2017

Edit Values
FastMATH 3 GHz
General Info
DesignerIntrinsity
ManufacturerTSMC
Model NumberFastMATH-3
MarketEmbedded
Introduction2003 (announced)
General Specs
FamilyFastMATH
Frequency3,000 MHz
Bus typeRapidIO
Bus speed500 MHz
Bus rate4 GT/s
Microarchitecture
MicroarchitectureFashMATH
Process130 nm
TechnologyDynamic CMOS
Word Size32 bit
Cores1
Threads1
Max Memory1 GiB
Electrical
Vcore1.25 V

The FastMATH 3 GHz was a microprocessor developed by Intrinsity operating at 3 GHz. The processor incorporates a high-performance MIPS CPU along with a powerful matrix and vector math unit.

Cache[edit]

Main article: FastMATH § Cache
Cache Info [Edit Values]
L1I$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 256 blocks × 16 words/block
L1D$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 256 blocks × 16 words/block write-through or write-back mode
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
1x1 MiB 4-way set associative (configurable as SRAM in 256 KiB increments)

Graphics[edit]

This SoC has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR-400
Controllers 1
Channels 2
Max memory 1 GB

Matrix and Vector Unit[edit]

  • SIMD architecture
  • Operates on 4x4 array of 32-bit elements
  • Fixed-point matrix, vector, and scalar data types

Features[edit]

  • JTAG interface
  • 8-bit or 32-bit wide bus operates up to 66 MHz


Retrieved from "https://en.wikichip.org/w/index.php?title=intrinsity/fastmath/fastmath-3&oldid=71120"
Facts about "FastMATH 3 GHz - Intrinsity"
RDF feed
base frequency3,000 MHz (3 GHz, 3,000,000 kHz) +
bus rate4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus speed500 MHz (0.5 GHz, 500,000 kHz) +
bus typeRapidIO +
core count1 +
core voltage1.25 V (12.5 dV, 125 cV, 1,250 mV) +
designerIntrinsity +
familyFastMATH +
first announced2003 +
full page nameintrinsity/fastmath/fastmath-3 +
has featureJTAG +
instance ofmicroprocessor +
l1d$ description256 blocks × 16 words/block +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description256 blocks × 16 words/block +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate2003 +
manufacturerTSMC +
market segmentEmbedded +
max memory1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
microarchitectureFashMATH +
model numberFastMATH-3 +
nameFastMATH 3 GHz +
process130 nm (0.13 μm, 1.3e-4 mm) +
technologyDynamic CMOS +
thread count1 +
word size32 bit (4 octets, 8 nibbles) +