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== Members ==
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<table class="wikitable sortable">
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<tr><th colspan="10" style="background:#D6D6FF;">FastMATH Processors</th></tr>
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<tr><th>Model</th><th>µarch</th><th>Process</th><th>Launched</th><th>Frequency</th><th>Power</th><th>Memory</th><th>V<sub>CORE</sub></th></tr>
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{{#ask: [[Category:microprocessor models by intrinsity]] [[instance of::microprocessor]] [[microprocessor family::FastMATH]]
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== Documents ==
 
== Documents ==
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[[File:eval board.jpg|right|thumb|Evaluation Board]]
  
 
=== Manuals ===
 
=== Manuals ===
 
* [[:File:FastMATH Product Brief.pdf|FastMATH Product Brief]]
 
* [[:File:FastMATH Product Brief.pdf|FastMATH Product Brief]]
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* [[:File:fastmath evaluation board technical summary.pdf|FastMATH evaluation board technical summary]]
  
 
=== White Paper ===
 
=== White Paper ===
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* [[:File:Intrinsity Symbol Rate Processing.pdf|Symbol Rate Processing]]
 
* [[:File:Intrinsity Symbol Rate Processing.pdf|Symbol Rate Processing]]
 
* [[:File:Intrinsity Timing of Single Threaded Application.pdf|Timing of Single Threaded Application]]
 
* [[:File:Intrinsity Timing of Single Threaded Application.pdf|Timing of Single Threaded Application]]
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=== Others ===
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* [[:File:FastMATH.ppt|FastMATH Presentation]]

Latest revision as of 16:41, 3 July 2016

FastMATH
fastmath chip.jpg
FastMATH and FastMIPS chips
Developer Intrinsity
Manufacturer TSMC
Type Microprocessors
Introduction 2000 (announced)
2002 (launch)
Architecture 32-bit vector/matrix math processor + RISC cpu
Word size 32 bit
4 octets
8 nibbles
Process 130 nm
0.13 μm
1.3e-4 mm
Technology CMOS
Clock 1 GHz-3 GHz
Package CBGA-670

FastMATH was a family of matrix and vector math processors with an on-die RISC CPUs introduced by Intrinsity. The chips were developed using Intrinsity's own proprietary Fast14 technology.

Architecture[edit]

Main article: FastMATH Microarchitecture

FastMATH was a series of microprocessors developed by Intrinsity using Fast14 technology - i.e. processors designed using custom dynamic domino logic. These chips incorporate the FastMIPS core along with a custom high-performance matrix and vector math coprocessor.

Matrix and Vector Math Processing Unit[edit]

The unit is designed as a single-instruction, multiple-data (SIMD) architecture capable of oeprating on 4x4 arrays of 32-bit values. Operates support fixed-point matrix, vector, and scalar data types with dedicated local register file. Data arrays are directly fetched from L2 cache.

  • Zero-cycle latency, two-cycle throughput
  • 64 GOPS (peak) at 2 GHz
  • 551,000 radix-4 1024-point 16-bit FFTs/sec at 2 GHz
  • 32 GMACs/sec at 2 GHz
New text document.svg This section requires expansion; you can help adding the missing info.

Members[edit]

FastMATH Processors
ModelµarchProcessLaunchedFrequencyPowerMemoryVCORE
FastMATH-1.5FashMATH130 nm
0.13 μm
1.3e-4 mm
20021.5 GHz
1,500 MHz
1,500,000 kHz
13.5 W
13,500 mW
0.0181 hp
0.0135 kW
1,024 MiB
1,048,576 KiB
1,073,741,824 B
1 GiB
9.765625e-4 TiB
1 V
10 dV
100 cV
1,000 mV
FastMATH-2FashMATH130 nm
0.13 μm
1.3e-4 mm
20022 GHz
2,000 MHz
2,000,000 kHz
15 W
15,000 mW
0.0201 hp
0.015 kW
1,024 MiB
1,048,576 KiB
1,073,741,824 B
1 GiB
9.765625e-4 TiB
1 V
10 dV
100 cV
1,000 mV
FastMATH-3FashMATH130 nm
0.13 μm
1.3e-4 mm
3 GHz
3,000 MHz
3,000,000 kHz
1,024 MiB
1,048,576 KiB
1,073,741,824 B
1 GiB
9.765625e-4 TiB
1.25 V
12.5 dV
125 cV
1,250 mV
FastMATH-LPFashMATH130 nm
0.13 μm
1.3e-4 mm
20031 GHz
1,000 MHz
1,000,000 kHz
6 W
6,000 mW
0.00805 hp
0.006 kW
1,024 MiB
1,048,576 KiB
1,073,741,824 B
1 GiB
9.765625e-4 TiB
0.85 V
8.5 dV
85 cV
850 mV
Count: 4


Documents[edit]

Evaluation Board

Manuals[edit]

White Paper[edit]

Others[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intrinsity/fastmath&oldid=22696"
Facts about "FastMATH - Intrinsity"
RDF feed
designerIntrinsity +
first announced2000 +
first launched2002 +
full page nameintrinsity/fastmath +
instance ofmicroprocessor family +
main designerIntrinsity +
manufacturerTSMC +
nameFastMATH +
packageCBGA-670 +
process130 nm (0.13 μm, 1.3e-4 mm) +
technologyCMOS +
word size32 bit (4 octets, 8 nibbles) +