From WikiChip
Difference between revisions of "exponential technology/x704/410"
< exponential technology‎ | x704

(Created page with "{{expotech title|X704-410}} {{mpu | name = X704-410 | no image = Yes | image = | image size = | caption = | des...")
 
m (Bot: moving all {{mpu}} to {{chip}})
 
(4 intermediate revisions by 3 users not shown)
Line 1: Line 1:
 
{{expotech title|X704-410}}
 
{{expotech title|X704-410}}
−
{{mpu
+
{{chip
 
| name                = X704-410
 
| name                = X704-410
 
| no image            = Yes
 
| no image            = Yes
Line 11: Line 11:
 
| part number        =  
 
| part number        =  
 
| market              = Desktop
 
| market              = Desktop
−
| first announced    = January 7, 1997
+
| first announced    =  
 
| first launched      = March, 1997
 
| first launched      = March, 1997
 
| last order          = March, 1997
 
| last order          = March, 1997
Line 43: Line 43:
 
| max memory addr    =  
 
| max memory addr    =  
  
−
| electrical          = Yes
+
 
 
| power              = 85 W
 
| power              = 85 W
 
| v core              = 3.6 V
 
| v core              = 3.6 V
Line 73: Line 73:
 
| socket 0 type      = BGA
 
| socket 0 type      = BGA
 
}}
 
}}
−
'''X704 410 MHz''' was a [[PowerPC]]-compatible microprocessor operating at 410 MHz introduced in February of [[1997]]. This model was the final and only model actually produced by [[Exponential Technology]] in early 1997 with the plan of being implemented by [[Apple]] in their machines. The model was later dropped by Apple and faded into obscurity.
+
'''X704 410 MHz''' was a [[PowerPC]]-compatible microprocessor operating at 410 MHz introduced in February of [[1997]]. This model was the final and only model actually produced by [[Exponential Technology]] in early 1997 with the plan of being implemented by [[Apple]] in their machines. The model was later dropped by Apple and faded into obscurity (See [[exponential_technology/x704#History|X704 § History]]).
 +
 
 +
== Cache ==
 +
{{main|exponential_technology/microarchitectures/x704#Memory_Hierarchy|l1=X704 § Cache}}
 +
Level 3 can be provided externally with cache size of 512 KiB to 2 MiB.
 +
{{cache info
 +
|l1i cache=2 KiB
 +
|l1i break=1x2 KiB
 +
|l1i desc=direct mapped
 +
|l1i extra=
 +
|l1d cache=2 KiB
 +
|l1d break=1x2 KiB
 +
|l1d desc=direct mapped
 +
|l1d extra=
 +
|l2 cache=32 KiB
 +
|l2 break=1x32 KiB
 +
|l2 desc=8-way set associative
 +
|l2 extra=
 +
|l3 cache=
 +
|l3 break=
 +
|l3 desc=
 +
|l3 extra=
 +
}}
 +
 
 +
== Graphics ==
 +
This SoC has no integrated graphics processing unit.
 +
 
 +
== Features ==
 +
* Fully PowerPC 60x-compatible architecture
 +
* IEEE 1149.1-compliant JTAG test access port
 +
* IEEE 754-compliant single-precision and double-precision arithmetic
 +
* Support for standard PowerPC 60X bus with 64 bits of data and 32 bits of address
 +
* Support for all PowerPC cache operations
 +
* Support for PowerEndian and BigEndian modes
 +
 
 +
== Documents ==
 +
 
 +
=== Manuals ===
 +
* [[:File:X704 technical summary.pdf|X704 Technical Summary]], 1996
 +
 
 +
== See also ==
 +
* [[PowerPC]]
 +
* {{expotech|X704}}

Latest revision as of 15:13, 13 December 2017

Edit Values
X704-410
General Info
DesignerExponential Technology
ManufacturerHitachi
Model NumberX704-410
MarketDesktop
IntroductionMarch, 1997 (launched)
End-of-lifeMarch, 1997 (last order)
March, 1997 (last shipment)
General Specs
FamilyX704
Frequency410 MHz
Bus type60x bus
Bus speed100 MHz
Clock multiplier4.1
Microarchitecture
MicroarchitectureX704
PlatformCHRP
Process500 nm
Transistors2,700,000
TechnologyBiCMOS
Die150 mm²
Word Size32 bit
Cores1
Threads1
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation85 W
Vcore3.6 V

X704 410 MHz was a PowerPC-compatible microprocessor operating at 410 MHz introduced in February of 1997. This model was the final and only model actually produced by Exponential Technology in early 1997 with the plan of being implemented by Apple in their machines. The model was later dropped by Apple and faded into obscurity (See X704 § History).

Cache[edit]

Main article: X704 § Cache

Level 3 can be provided externally with cache size of 512 KiB to 2 MiB.

Cache Info [Edit Values]
L1I$ 2 KiB
2,048 B
0.00195 MiB
1x2 KiB direct mapped
L1D$ 2 KiB
2,048 B
0.00195 MiB
1x2 KiB direct mapped
L2$ 32 KiB
0.0313 MiB
32,768 B
3.051758e-5 GiB
1x32 KiB 8-way set associative

Graphics[edit]

This SoC has no integrated graphics processing unit.

Features[edit]

  • Fully PowerPC 60x-compatible architecture
  • IEEE 1149.1-compliant JTAG test access port
  • IEEE 754-compliant single-precision and double-precision arithmetic
  • Support for standard PowerPC 60X bus with 64 bits of data and 32 bits of address
  • Support for all PowerPC cache operations
  • Support for PowerEndian and BigEndian modes

Documents[edit]

Manuals[edit]

See also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=exponential_technology/x704/410&oldid=70332"
Facts about "X704-410 - Exponential Technology"
RDF feed
base frequency410 MHz (0.41 GHz, 410,000 kHz) +
bus speed100 MHz (0.1 GHz, 100,000 kHz) +
bus type60x bus +
clock multiplier4.1 +
core count1 +
core voltage3.6 V (36 dV, 360 cV, 3,600 mV) +
designerExponential Technology +
die area150 mm² (0.233 in², 1.5 cm², 150,000,000 µm²) +
familyX704 +
first launchedMarch 1997 +
full page nameexponential technology/x704/410 +
instance ofmicroprocessor +
l1d$ descriptiondirect mapped +
l1d$ size2 KiB (2,048 B, 0.00195 MiB) +
l1i$ descriptiondirect mapped +
l1i$ size2 KiB (2,048 B, 0.00195 MiB) +
l2$ description8-way set associative +
l2$ size0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) +
last orderMarch 1997 +
last shipmentMarch 1997 +
ldateMarch 1997 +
manufacturerHitachi +
market segmentDesktop +
max cpu count1 +
microarchitectureX704 +
model numberX704-410 +
nameX704-410 +
platformCHRP +
power dissipation85 W (85,000 mW, 0.114 hp, 0.085 kW) +
process500 nm (0.5 μm, 5.0e-4 mm) +
smp max ways1 +
technologyBiCMOS +
thread count1 +
transistor count2,700,000 +
word size32 bit (4 octets, 8 nibbles) +