Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "ambric/am2000/am2012"
m (Bot: switching template from {{mpu}} to a more generic {{chip}}) |
|||
| (5 intermediate revisions by 2 users not shown) | |||
| Line 1: | Line 1: | ||
{{ambric title|Am2012}} | {{ambric title|Am2012}} | ||
| − | {{ | + | {{chip |
| name = Am2012 | | name = Am2012 | ||
| no image = Yes | | no image = Yes | ||
| Line 11: | Line 11: | ||
| part number = Am2012 | | part number = Am2012 | ||
| market = Embedded | | market = Embedded | ||
| − | | first announced = | + | | first announced = October 10, 2006 |
| − | | first launched = | + | | first launched = January 2007 |
| last order = 2012 | | last order = 2012 | ||
| last shipment = 2012 | | last shipment = 2012 | ||
| Line 21: | Line 21: | ||
| frequency = 333 MHz | | frequency = 333 MHz | ||
| bus type = | | bus type = | ||
| − | | bus speed = | + | | bus speed = 100 MHz |
| bus rate = | | bus rate = | ||
| − | | clock multiplier = | + | | clock multiplier = 3.3 |
| microarch = Ambric | | microarch = Ambric | ||
| Line 40: | Line 40: | ||
| thread count = | | thread count = | ||
| max cpus = | | max cpus = | ||
| − | | max memory = | + | | max memory = 4 GiB |
| electrical = | | electrical = | ||
| Line 72: | Line 72: | ||
| socket 0 type = | | socket 0 type = | ||
}} | }} | ||
| + | '''Am2012''' was an [[MPPA]] introduced in late 2006 by [[Ambric]]. This model was made of {{ambric|am2000#Architecture|12 Brics}} arranged as a grid, making up a total of 96 {{arch|32}} [[RICS]]-like cores operating asynchronously at 1-333 MHz. | ||
| + | |||
| + | == Architecture == | ||
| + | {{main|ambric/am2000#Architecture|l1=Am2000 § Architecture}} | ||
| + | The Am2012 is made of 12 homogeneous 'Brics' laid out in a grid to form 96 cores and 96 RAM units. | ||
| + | |||
| + | General layout: | ||
| + | * 12x Brics | ||
| + | ** 2x Computer Unit (CU) | ||
| + | *** 2x SRD {{arch|32}} CPU | ||
| + | *** 2x RD {{arch|32}} CPU | ||
| + | ** 2x [[RAM]] Unit (RU) | ||
| + | *** 4x 2 KB [[SRAM]] bank | ||
| + | |||
| + | == Cache == | ||
| + | The Am2012 contains 12 Brics, each with its own [[RAM]] Unit (RU) of 13 kB of SRAM for a total of 156 kB of SRAM. | ||
| + | |||
| + | == Memory controller == | ||
| + | {{integrated memory controller | ||
| + | | type = DDR2-400 | ||
| + | | controllers = 2 | ||
| + | | channels = 1 | ||
| + | | ecc support = | ||
| + | | max bandwidth = | ||
| + | | bandwidth schan = | ||
| + | | bandwidth dchan = | ||
| + | | max memory = 4 GiB | ||
| + | }} | ||
| + | |||
| + | == Expansions == | ||
| + | * [[has feature::PCIe]] | ||
| + | * [[has feature::JTAG]] | ||
| + | * [[has feature::GPIO]] @ 100 MHz | ||
| + | * [[has feature::serial flash]] | ||
Latest revision as of 14:16, 13 December 2017
| Edit Values | |
| Am2012 | |
| General Info | |
| Designer | Ambric |
| Model Number | Am2012 |
| Part Number | Am2012 |
| Market | Embedded |
| Introduction | October 10, 2006 (announced) January 2007 (launched) |
| End-of-life | 2012 (last order) 2012 (last shipment) |
| General Specs | |
| Family | Am2000 |
| Series | Gen 1 |
| Locked | No |
| Frequency | 333 MHz |
| Bus speed | 100 MHz |
| Clock multiplier | 3.3 |
| Microarchitecture | |
| Microarchitecture | Ambric |
| Process | 130 nm |
| Technology | CMOS |
| Word Size | 32 bit |
| Cores | 96 |
| Max Memory | 4 GiB |
Am2012 was an MPPA introduced in late 2006 by Ambric. This model was made of 12 Brics arranged as a grid, making up a total of 96 32-bit RICS-like cores operating asynchronously at 1-333 MHz.
Architecture[edit]
- Main article: Am2000 § Architecture
The Am2012 is made of 12 homogeneous 'Brics' laid out in a grid to form 96 cores and 96 RAM units.
General layout:
- 12x Brics
Cache[edit]
The Am2012 contains 12 Brics, each with its own RAM Unit (RU) of 13 kB of SRAM for a total of 156 kB of SRAM.
Memory controller[edit]
| Integrated Memory Controller | |
| Type | DDR2-400 |
| Controllers | 2 |
| Channels | 1 |
| Max memory | 4 GiB |
Expansions[edit]
- PCIe
- JTAG
- GPIO @ 100 MHz
- serial flash