Difference between revisions of "samsung/exynos/8895"

	Edit Values
	Exynos 8895
	General Info
Designer	Samsung,; ARM Holdings
Manufacturer	Samsung
Model Number	8895
Market	Mobile
Introduction	February 23, 2017 (announced); March 29, 2017 (launched)
	General Specs
Family	Exynos
Series	Exynos 9
Locked	No
Frequency	2314 MHz, 1690 MHz
Turbo Frequency	2808 MHz
Turbo Frequency	1690 MHz (1 core),; 1690 MHz (2 cores),; 1690 MHz (3 cores),; 1690 MHz (4 cores),; 2314 MHz (5 cores),; 2314 MHz (6 cores),; 2314 MHz (7 cores),; 2314 MHz (8 cores)
Bus type	exynos-ossclk (FSB)
Bus speed	26MHz
Bus rate	3? × 8GT/s
Clock multiplier	108
CPUID	universal8895
	Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	M2, Cortex-A53
Platform	universal8895
Chipset	Exynos 8895
Core Name	Mongoose 2, Cortex-A53
Core Family	Samsung Mongoose, ARM Cortex
Core Model	Samsung Mongoose 2, Cortex A53
Process	10 nm
Technology	CMOS
MCP	No
Word Size	64 bit
Cores	8
Threads	8
Max Memory	8 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Electrical
Vcore	0.7 V-1.3 V
VI/O	1.02 V
TDP	8 W
cTDP down	8 W
cTDP down frequency	2314 MHz
cTDP up	16 W
cTDP up frequency	2808 MHz
OP Temperature	-15 °C – 115 °C
Tjunction	110 – 115
	Succession
	Exynos 8890 Exynos 9810
	Contemporary
	Exynos 9820

Latest revision as of 06:19, 16 May 2024

Exynos 8895 is a 64-bit octa-core ARM high performance mobile system on a chip designed by Samsung and introduced in mid-2017. The processor is fabricated on Samsung's 10nm EUV (Extreme Ultra Violet) FinFET process and features 8 cores in a dual-cluster configuration consisting of 4 Mongoose 2 big cores commonly running at 2314 (but can go up to 2808 MHz), 4 Cortex-A53 little cores at 1690 (to 2002 MHz). This chip supports up to 8 GiB of dual-channel 16-bit LPDDR4X-1796 memory and incorporates a Mali-G71 MP20 GPU running at 546MHz. The 8895 incorporates an LTE modem supporting cat 16 download and upload.

Cache[edit]

Main articles: Mongoose 2 § Cache and Cortex-A53 § Cache

For the Mongoose 2 core cluster:

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

192 KiB

196,608 B
0.188 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	2x64 KiB	4-way set associative
L1D$	64 KiB 65,536 B 0.0625 MiB	2x32 KiB	8-way set associative

L2$

1 MiB

1,024 KiB
1,048,576 B
9.765625e-4 GiB

		2x512 KiB	16-way set associative

L3$

2 MiB

2,048 KiB
2,097,152 B
0.00195 GiB

		2x1 MiB

For the Cortex-A53 cluster:

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

256 KiB

262,144 B
0.25 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	2x64 KiB	4-way set associative
L1D$	128 KiB 131,072 B 0.125 MiB	2x64 KiB	16-way set associative

L2$

512 KiB

0.5 MiB
524,288 B
4.882812e-4 GiB

		2x256 KiB	8-way set associative

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	LPDDR4X-1796
Supports ECC	No
Max Mem	8 GiB
Frequency	1794 MHz
Controllers	2
Channels	2
Width	32 bit
Max Bandwidth	28.70 GB/s 26.729 GiB/s 27,370.453 MiB/s 28,700 MB/s 0.0261 TiB/s 0.0287 TB/s
Bandwidth	Single 14.32 GB/s Double 28.64 GB/s

Graphics[edit]

[Edit/Modify IGP Info]

Integrated Graphics Information

GPU

Mali-G71

Designer

ARM Holdings

Execution Units

20

Max Displays

2

Frequency

546 MHz

0.546 GHz
546,000 KHz

Burst Frequency

839 MHz

0.839 GHz
839,000 KHz

Output

DSI

Standards

DirectX	12
OpenCL	2
OpenGL ES	3.2
OpenVG	1.1
Vulkan	1.0

Codec	Encode	Decode150
HEVC (H.265)	✔	✔
MPEG-4 AVC (H.264)	✔	✔
VP9	✔	✔

All at 4K UHD 60fps.

Wireless[edit]

Wireless Communications

Cellular

4G

LTE Advanced

UE Cat DL	16 (1000 Mbps)
UE Cat UL	16 (280 Mbps)

ISP[edit]

28MP Rear
16MP Front
28MP+28MP Dual

Features[edit]

[Edit/Modify Supported Features]

Supported ARM Extensions & Processor Features

NEON	Advanced SIMD extension
CRC32	CRC-32 checksum Extension
Crypto	Cryptographic Extension
FP	Floating-point Extension

Utilizing devices[edit]

Samsung Galaxy Note 8
Samsung Galaxy S8
Samsung Galaxy S8+

@@ Line 15: / Line 15: @@
 |frequency=2314 MHz
 |frequency 2=1690 MHz
+|turbo frequency1=1690 MHz
+|turbo frequency2=1690 MHz
+|turbo frequency3=1690 MHz
+|turbo frequency4=1690 MHz
+|turbo frequency5=2314 MHz
+|turbo frequency6=2314 MHz
+|turbo frequency7=2314 MHz
+|turbo frequency8=2314 MHz
+|turbo frequency 2=2002 MHz
+|turbo frequency=2808 MHz
+|bus type=exynos-ossclk (FSB)
+|bus speed=26MHz
+|bus links=3?
+|bus rate=8GT/s
+|clock multiplier=108
+|cpuid=universal8895
 |isa=ARMv8
 |isa family=ARM
 |microarch=M2
 |microarch 2=Cortex-A53
-|core name=Exynos M2
+|platform=universal8895
+|chipset=Exynos 8895
+|core name=Mongoose 2
 |core name 2=Cortex-A53
+|core name 4=2nd generation
+|core family=Samsung Mongoose
+|core family 2=ARM Cortex
+|core model=Samsung Mongoose 2
+|core model 2=Cortex A53
 |process=10 nm
 |technology=CMOS
-|mcp=Yes
+|mcp=No
 |word size=64 bit
 |core count=8
@@ Line 29: / Line 52: @@
 |max memory=8 GiB
 |max cpus=1
-|v core min=0.905 V
+|v core min=0.7 V
-|v core max=1.22 V
+|v core max=1.3 V
-|tdp=5 W
+|v io=1.02 V
-|ctdp down=12 W
+|tdp=8 W
+|ctdp down=8 W
 |ctdp down frequency=2314 MHz
 |ctdp up=16 W
-|ctdp up frequency=2810 MHz
+|ctdp up frequency=2808 MHz
 |temp min=-15 °C
 |temp max=115 °C
-|tjunc min=115
+|tjunc min=110
 |tjunc max=115
 |predecessor=Exynos 8890
@@ Line 47: / Line 71: @@
 |contemporary link=samsung/exynos/9820
 }}
-'''Exynos 8895''' is a {{arch|64}} [[octa-core]] [[ARM]] high performance mobile [[system on a chip]] designed by [[Samsung]] and introduced in mid-[[2019]]. The processor is fabricated on Samsung's [[10 nm process|10nm]] EUV (Extreme Ultra Violet) FinFET process and features [[8 cores]] in a tri-cluster configuration consisting of 4 {{samsung|Mongoose 2|l=arch}} [[big cores]] running at 2314 to 2810 MHz, 4 {{armh|Cortex-A53|l=arch}} [[little cores]] at 1690 to 2002 MHz. This chip supports up to 8 GiB of dual-channel 16-bit LPDDR4X-1794 memory and incorporates a {{armh|Mali-G71}} MP20 GPU. The 8895 incorporates an LTE modem supporting cat 16 download and upload.
+'''Exynos 8895''' is a {{arch|64}} [[octa-core]] [[ARM]] high performance mobile [[system on a chip]] designed by [[Samsung]] and introduced in mid-[[2017]]. The processor is fabricated on Samsung's [[10 nm process|10nm]] EUV (Extreme Ultra Violet) FinFET process and features [[8 cores]] in a dual-cluster configuration consisting of 4 {{samsung|Mongoose 2|l=arch}} [[big cores]] commonly running at 2314 (but can go up to 2808 MHz), 4 {{armh|Cortex-A53|l=arch}} [[little cores]] at 1690 (to 2002 MHz). This chip supports up to 8 GiB of dual-channel 16-bit LPDDR4X-1796 memory and incorporates a {{armh|Mali-G71}} MP20 GPU running at 546MHz. The 8895 incorporates an LTE modem supporting cat 16 download and upload.
 == Cache ==
-{{main|samsung/microarchitectures/m2#Memory_Hierarchy|arm_holdings/microarchitectures/m2#Memory_Hierarchy|l1=Mongoose 2  § Cache||l2=Cortex-A53 § Cache}}
+{{main|samsung/microarchitectures/m2#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Mongoose 2  § Cache||l2=Cortex-A53 § Cache}}
 For the {{samsung|Mongoose 2|l=arch}} core cluster:
 {{cache size
@@ Line 84: / Line 108: @@
 == Memory controller ==
 {{memory controller
-|type=LPDDR4X-3588
+|type=LPDDR4X-1796
 |ecc=No
 |max mem=8 GiB
@@ Line 90: / Line 114: @@
 |channels=2
 |width=32 bit
-|max bandwidth=28.64 GiB/s
+|max bandwidth=28.70 GB/s
-|frequency=1800 MHz
+|frequency=1794 MHz
-|bandwidth schan=14.32 GiB/s
+|bandwidth schan=14.32 GB/s
-|bandwidth dchan=28.64 GiB/s
+|bandwidth dchan=28.64 GB/s
 }}
@@ Line 105: / Line 129: @@
 | max memory          =
 | frequency           = 546 MHz
-| max frequency       = 850 MHz
+| max frequency       = 839 MHz
 | output crt          =

base frequency	2,314 MHz (2.314 GHz, 2,314,000 kHz) + and 1,690 MHz (1.69 GHz, 1,690,000 kHz) +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus speed	26 MHz (0.026 GHz, 26,000 kHz) +
bus type	exynos-ossclk (FSB) +
chipset	Exynos 8895 +
clock multiplier	108 +
core count	8 +
core family	Samsung Mongoose + and ARM Cortex +
core model	Samsung Mongoose 2 + and Cortex A53 +
core name	Mongoose 2 + and Cortex-A53 +
core voltage (max)	1.3 V (13 dV, 130 cV, 1,300 mV) +
core voltage (min)	0.7 V (7 dV, 70 cV, 700 mV) +
cpuid	universal8895 +
designer	Samsung + and ARM Holdings +
family	Exynos +
first announced	February 23, 2017 +
first launched	March 29, 2017 +
full page name	samsung/exynos/8895 +
has 4g support	true +
has ecc memory support	false +
has locked clock multiplier	false +
has lte advanced support	true +
instance of	microprocessor +
integrated gpu	Mali-G71 +
integrated gpu base frequency	546 MHz (0.546 GHz, 546,000 KHz) +
integrated gpu designer	ARM Holdings +
integrated gpu execution units	20 +
integrated gpu max frequency	839 MHz (0.839 GHz, 839,000 KHz) +
io voltage	1.02 V (10.2 dV, 102 cV, 1,020 mV) +
is multi-chip package	false +
isa	ARMv8 +
isa family	ARM +
l1$ size	192 KiB (196,608 B, 0.188 MiB) + and 256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	8-way set associative + and 16-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) + and 128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	4-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	16-way set associative + and 8-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + and 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate	March 29, 2017 +
manufacturer	Samsung +
market segment	Mobile +
max cpu count	1 +
max junction temperature	115 K (-158.15 °C, -252.67 °F, 207 °R) +
max memory	8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) +
max memory bandwidth	26.729 GiB/s (27,370.453 MiB/s, 28.7 GB/s, 28,700 MB/s, 0.0261 TiB/s, 0.0287 TB/s) +
max memory channels	2 +
max operating temperature	115 °C +
microarchitecture	M2 + and Cortex-A53 +
min junction temperature	110 K (-163.15 °C, -261.67 °F, 198 °R) +
min operating temperature	-15 °C +
model number	8895 +
name	Exynos 8895 +
platform	universal8895 +
process	10 nm (0.01 μm, 1.0e-5 mm) +
series	Exynos 9 +
smp max ways	1 +
supported memory type	LPDDR4X-1796 +
tdp	8 W (8,000 mW, 0.0107 hp, 0.008 kW) +
tdp down	8 W (8,000 mW, 0.0107 hp, 0.008 kW) +
tdp down frequency	2,314 MHz (2.314 GHz, 2,314,000 kHz) +
tdp up	16 W (16,000 mW, 0.0215 hp, 0.016 kW) +
tdp up frequency	2,808 MHz (2.808 GHz, 2,808,000 kHz) +
technology	CMOS +
thread count	8 +
turbo frequency	2,808 MHz (2.808 GHz, 2,808,000 kHz) +
turbo frequency (1 core)	1,690 MHz (1.69 GHz, 1,690,000 kHz) +
turbo frequency (2 cores)	1,690 MHz (1.69 GHz, 1,690,000 kHz) +
turbo frequency (3 cores)	1,690 MHz (1.69 GHz, 1,690,000 kHz) +
turbo frequency (4 cores)	1,690 MHz (1.69 GHz, 1,690,000 kHz) +
turbo frequency (5 cores)	2,314 MHz (2.314 GHz, 2,314,000 kHz) +
turbo frequency (6 cores)	2,314 MHz (2.314 GHz, 2,314,000 kHz) +
turbo frequency (7 cores)	2,314 MHz (2.314 GHz, 2,314,000 kHz) +
turbo frequency (8 cores)	2,314 MHz (2.314 GHz, 2,314,000 kHz) +
used by	Samsung Galaxy Note 8 +, Samsung Galaxy S8 + and Samsung Galaxy S8+ +
user equipment category downlink	16 +
user equipment category uplink	16 +
word size	64 bit (8 octets, 16 nibbles) +

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