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{{samsung title|Exynos 5433}}
 
{{samsung title|Exynos 5433}}
 
{{chip
 
{{chip
 +
|chip type=integrated circuit
 
|name=Exynos 5433
 
|name=Exynos 5433
 
|no image=Yes
 
|no image=Yes
Line 14: Line 15:
 
|frequency=1,900 MHz
 
|frequency=1,900 MHz
 
|frequency 2=1,300 MHz
 
|frequency 2=1,300 MHz
 +
|frequency 3=2,340 MHz
 +
|frequency 4=1,101 MHz
 
|isa=ARMv8
 
|isa=ARMv8
 
|isa family=ARM
 
|isa family=ARM
Line 22: Line 25:
 
|process=20 nm
 
|process=20 nm
 
|technology=CMOS
 
|technology=CMOS
 +
|die area=113 mm²
 
|word size=64 bit
 
|word size=64 bit
 
|core count=8
 
|core count=8
 
|thread count=8
 
|thread count=8
 
|max cpus=1
 
|max cpus=1
 +
|v core min=1.00 V
 +
|ctdp down=12 W
 +
|ctdp down frequency=1,900 MHz
 +
|ctdp up=18 W
 +
|ctdp up frequency=2,340 MHz
 +
|tjunc min=100°C
 
}}
 
}}
 +
'''Exynos 5433''' is a {{arch|64}} [[octa-core]] [[ARM]] high performance mobile [[system on a chip]] designed by [[Samsung]] and introduced in early [[2014]]. The processor is fabricated on Samsung's [[20 nm]] process and features [[8 cores]] in a {{armh|big.LITTLE}} configuration consisting of 4 {{armh|Cortex-A57|l=arch}} [[big cores]] and 4 {{armh|Cortex-A53|l=arch}} [[little cores]]. This chip supports up to 3 GiB of dual-channel LPDDR3-1866 memory and incorporates a {{armh|Mali-T760}} MP6 GPU.
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== Cache ==
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{{main|arm_holdings/microarchitectures/cortex-a57#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Cortex-A57 § Cache|l2=Cortex-A53 § Cache}}
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 +
Cortex-A57 Cluster:
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 +
{{cache size
 +
|l1 cache=320 KiB
 +
|l1i cache=192 KiB
 +
|l1i break=4x48 KiB
 +
|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
 +
|l2 cache=2 MiB
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|l2 break=1x2 MiB
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}}
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 +
Cortex-A53 Cluster:
 +
 +
{{cache size
 +
|l1 cache=256 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
 +
|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
 +
|l2 cache=256 KiB
 +
|l2 break=1x1 256 KiB
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}}
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== Memory controller ==
 +
{{memory controller
 +
|type=LPDDR3-1866
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|ecc=No
 +
|max mem=3 GiB
 +
|controllers=1
 +
|channels=2
 +
|width=32 bit
 +
|max bandwidth=13.91 GiB/s
 +
|bandwidth schan=6.95 GiB/s
 +
|bandwidth dchan=13.91 GiB/s
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}}
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 +
== Graphics ==
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{{integrated graphics
 +
| gpu                = Mali-T760
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| device id          =
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| designer            = ARM Holdings
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| execution units    = 6
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| max displays        = 2
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| max memory          =
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| frequency          = 700 MHz
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| max frequency      =
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| output crt          =
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| output sdvo        =
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| output dsi          =
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| output edp          =
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| output dp          =
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| output hdmi        =
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| output vga          =
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| output dvi          =
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| directx ver        = 11
 +
| opengl ver        =
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| opengl es ver      = 3.2
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| openvg ver        = 1.1
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| opencl ver        = 1.2
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| vulkan ver        = 1.0
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| hdmi ver          =
 +
| dp ver            =
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| edp ver            =
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| max res hdmi      =
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| max res hdmi freq  =
 +
| max res dp        =
 +
| max res dp freq    =
 +
| max res edp        =
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| max res edp freq  =
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| max res vga        =
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| max res vga freq  =
 +
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| max res generic    = 2560x1600
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}}
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* Full HD 120fps encoding and decoding
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* HEVC decoding, VP8 Codec
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== Camera ==
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* Front 3.7 MP
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* Rear 16 MP
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== Die ==
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* Samsung [[20 nm process]]
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* 113 mm² die size
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* Mali-T760 (6 EU)
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* Quad-core {{armh|Cortex-A53|l=arch}} ([[small cores]])
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** 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2
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** 4.4 mm² per cluster
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*** ~1 mm² per core
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*** ~0.55 mm² for 256 KiB L2 cache
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* Quad-core {{armh|Cortex-A57|l=arch}} ([[big cores]])
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** 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2
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** 15.85 mm² per cluster
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*** ~3 mm² per core
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*** ~3.87 mm² for 2 MiB L2 cache
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 +
 +
:[[File:exynos 5433 die.png|600px]]
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 +
== Utilizing devices ==
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* [[used by::Samsung Galaxy Note 4]]
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* [[used by::Samsung Galaxy Note Edge]]
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* [[used by::Samsung Galaxy Tab S2]]
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{{expand list}}
 +
 +
== Bibliography ==
 +
* Pyo, Jungyul, et al. "23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015

Latest revision as of 12:08, 6 March 2022

Edit Values
Exynos 5433
General Info
DesignerSamsung,
ARM Holdings
ManufacturerSamsung
Model Number5433
MarketMobile
IntroductionSeptember 7, 2014 (announced)
September 7, 2014 (launched)
General Specs
FamilyExynos
SeriesExynos 7
Frequency1,900 MHz, 1,300 MHz, 2,340 MHz, 1,101 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A57, Cortex-A53
Core NameCortex-A57, Cortex-A53
Process20 nm
TechnologyCMOS
Die113 mm²
Word Size64 bit
Cores8
Threads8
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1.00 V-
cTDP down12 W
cTDP down frequency1,900 MHz
cTDP up18 W
cTDP up frequency2,340 MHz
Tjunction100°C – 

Exynos 5433 is a 64-bit octa-core ARM high performance mobile system on a chip designed by Samsung and introduced in early 2014. The processor is fabricated on Samsung's 20 nm process and features 8 cores in a big.LITTLE configuration consisting of 4 Cortex-A57 big cores and 4 Cortex-A53 little cores. This chip supports up to 3 GiB of dual-channel LPDDR3-1866 memory and incorporates a Mali-T760 MP6 GPU.

Cache[edit]

Main articles: Cortex-A57 § Cache and Cortex-A53 § Cache


Cortex-A57 Cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$320 KiB
327,680 B
0.313 MiB
L1I$192 KiB
196,608 B
0.188 MiB
4x48 KiB  
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB  
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB  

Cortex-A53 Cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB  
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB  
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x1 256 KiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR3-1866
Supports ECCNo
Max Mem3 GiB
Controllers1
Channels2
Width32 bit
Max Bandwidth13.91 GiB/s
14,243.84 MiB/s
14.936 GB/s
14,935.749 MB/s
0.0136 TiB/s
0.0149 TB/s
Bandwidth
Single 6.95 GiB/s
Double 13.91 GiB/s

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-T760
DesignerARM Holdings
Execution Units6Max Displays2
Frequency700 MHz
0.7 GHz
700,000 KHz
Max Resolution
 2560x1600
Standards
DirectX11
OpenCL1.2
OpenGL ES3.2
OpenVG1.1
Vulkan1.0
  • Full HD 120fps encoding and decoding
  • HEVC decoding, VP8 Codec

Camera[edit]

  • Front 3.7 MP
  • Rear 16 MP

Die[edit]

  • Samsung 20 nm process
  • 113 mm² die size
  • Mali-T760 (6 EU)
  • Quad-core Cortex-A53 (small cores)
    • 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2
    • 4.4 mm² per cluster
      • ~1 mm² per core
      • ~0.55 mm² for 256 KiB L2 cache
  • Quad-core Cortex-A57 (big cores)
    • 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2
    • 15.85 mm² per cluster
      • ~3 mm² per core
      • ~3.87 mm² for 2 MiB L2 cache


exynos 5433 die.png

Utilizing devices[edit]

  • Samsung Galaxy Note 4
  • Samsung Galaxy Note Edge
  • Samsung Galaxy Tab S2

This list is incomplete; you can help by expanding it.

Bibliography[edit]

  • Pyo, Jungyul, et al. "23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015
Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/exynos/5433&oldid=99794"
Facts about "Exynos 5433 - Samsung"
RDF feed
base frequency1,900 MHz (1.9 GHz, 1,900,000 kHz) +, 1,300 MHz (1.3 GHz, 1,300,000 kHz) +, 2,340 MHz (2.34 GHz, 2,340,000 kHz) + and 1,101 MHz (1.101 GHz, 1,101,000 kHz) +
core count8 +
core nameCortex-A57 + and Cortex-A53 +
core voltage (min)1 V (10 dV, 100 cV, 1,000 mV) +
designerSamsung + and ARM Holdings +
die area113 mm² (0.175 in², 1.13 cm², 113,000,000 µm²) +
familyExynos +
first announcedSeptember 7, 2014 +
first launchedSeptember 7, 2014 +
full page namesamsung/exynos/5433 +
has ecc memory supportfalse +
instance ofintegrated circuit +
integrated gpuMali-T760 +
integrated gpu base frequency700 MHz (0.7 GHz, 700,000 KHz) +
integrated gpu designerARM Holdings +
integrated gpu execution units6 +
isaARMv8 +
isa familyARM +
l1$ size320 KiB (327,680 B, 0.313 MiB) + and 256 KiB (262,144 B, 0.25 MiB) +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ size192 KiB (196,608 B, 0.188 MiB) + and 128 KiB (131,072 B, 0.125 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + and 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldateSeptember 7, 2014 +
manufacturerSamsung +
market segmentMobile +
max cpu count1 +
max memory bandwidth13.91 GiB/s (14,243.84 MiB/s, 14.936 GB/s, 14,935.749 MB/s, 0.0136 TiB/s, 0.0149 TB/s) +
max memory channels2 +
microarchitectureCortex-A57 + and Cortex-A53 +
min junction temperature373.15 K (100 °C, 212 °F, 671.67 °R) +
model number5433 +
nameExynos 5433 +
process20 nm (0.02 μm, 2.0e-5 mm) +
seriesExynos 7 +
smp max ways1 +
supported memory typeLPDDR3-1866 +
tdp down12 W (12,000 mW, 0.0161 hp, 0.012 kW) +
tdp down frequency1,900 MHz (1.9 GHz, 1,900,000 kHz) +
tdp up18 W (18,000 mW, 0.0241 hp, 0.018 kW) +
tdp up frequency2,340 MHz (2.34 GHz, 2,340,000 kHz) +
technologyCMOS +
thread count8 +
used bySamsung Galaxy Note 4 +, Samsung Galaxy Note Edge + and Samsung Galaxy Tab S2 +
word size64 bit (8 octets, 16 nibbles) +