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|manufacturer=TSMC
 
|manufacturer=TSMC
 
|introduction=Oct 30, 2012
 
|introduction=Oct 30, 2012
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|isa=ARMv8
 
|predecessor=Cortex-A15
 
|predecessor=Cortex-A15
 
|predecessor link=arm_holdings/microarchitectures/cortex-a15
 
|predecessor link=arm_holdings/microarchitectures/cortex-a15
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'''Cortex-A57''' (codename '''Atlas''') is the successor to the {{armh|Cortex-A15|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A57, which implemented the {{arm|ARMv8}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A53}}) in a {{armh|big.LITTLE}} configuration to achieve better energy/performance.
 
'''Cortex-A57''' (codename '''Atlas''') is the successor to the {{armh|Cortex-A15|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A57, which implemented the {{arm|ARMv8}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A53}}) in a {{armh|big.LITTLE}} configuration to achieve better energy/performance.
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== Compiler support ==
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{| class="wikitable"
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|-
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! Compiler !! Arch-Specific || Arch-Favorable
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|-
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| [[Arm Compiler]] || <code>-mcpu=cortex-a57</code> || <code>-mtune=cortex-a57</code>
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|-
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| [[GCC]] || <code>-mcpu=cortex-a57</code> || <code>-mtune=cortex-a57</code>
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|-
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| [[LLVM]] || <code>-mcpu=cortex-a57</code> || <code>-mtune=cortex-a57</code>
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|}
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 +
If the Cortex-A57 is coupled with the {{\\|Cortex-A53}} in a [[big.LITTLE]] system, GCC also supports the following option:
 +
 +
{| class="wikitable"
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|-
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! Compiler !! Tune
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|-
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| [[GCC]] || <code>-mtune=cortex-a57.cortex-a53</code>
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|}
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== Architecture ==
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=== Key changes from {{\\|Cortex-A15}} ===
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{{empty section}}
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=== Block Diagram ===
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{{empty section}}
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=== Memory Hierarchy ===
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{{empty section}}
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== Die ==
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<table class="wikitable">
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<tr><th colspan="3">Cortex-A57 Clusters Silicon Areas (Estimated)</th></tr>
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<tr><th>Company</th><td>[[Samsung]]</td><td>[[Renesas]]</td></tr>
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<tr><th>Chip</th><td>[[Exynos 5433]]</td><td>[[R-Car H3]]</td></tr>
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<tr><th>Process</th><td>[[20 nm]]</td><td>[[16 nm]]</td></tr>
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<tr><th>Configuration</th><td>4x Cortex-A57<br>+ 2 MiB L2</td><td>4x Cortex-A57<br>+ 2 MiB L2</td></tr>
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<tr><th>Cluster Size</th><td>~15.85 mm²</td><td>~10.21 mm² cluster</td></tr>
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<tr><th>Core Size</th><td>~3 mm²</td><td>~1.66 mm² cluster</td></tr>
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<tr><th>Cache Size</th><td>~3.87 mm²</td><td>~3.28 mm² cluster</td></tr>
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</table>
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=== 20 nm ===
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==== Samsung [[Exynos 5433]] ====
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* Samsung [[20 nm process]]
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* 113 mm² die size
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* Mali-T760 (6 EU)
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* Quad-core {Primary Cortex-A57 [Quad] + Secondary A53 [Quad]}
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** 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2
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** 4.4 mm² per cluster
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*** ~1 mm² per core
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*** ~0.55 mm² for 256 KiB L2 cache
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* Quad-core Cortex-A57 ([[big cores]])
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** 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2
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** 15.85 mm² per cluster
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*** ~3 mm² per core
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*** ~3.87 mm² for 2 MiB L2 cache
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:[[File:exynos 5433 die.png|600px]]
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=== 16 nm ===
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==== Renesas [[R-Car H3]] ====
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* TSMC [[16 nm process]]
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* 12.94 mm × 8.61 mm
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* 111.36 mm² die size
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* Quad-core {{\\|Cortex-A53}}
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** ~3.27 mm² cluster
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** ~0.60 mm² core
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** ~0.7 mm² 512 KiB L2 cache
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* Quad-core Cortex-A57
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** ~10.21 mm² cluster
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** ~1.66 mm² core
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** ~3.28 mm² 2 MiB L2 cache
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* {{\\|Cortex-R7}} (dual-core [[lock-step]])
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** ~1.04 mm² cluster
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* GX6650 GPU
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** ~28.12 mm²
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: [[File:r-car h3 die shot.png|650px]]
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A57 Cluster:
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:[[File:h3 a57 cluster.png|400px]]
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== Bibliography ==
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* Pyo, Jungyul, et al. "23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015

Latest revision as of 20:13, 25 April 2021

Edit Values
Cortex-A57 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionOct 30, 2012
Instructions
ISAARMv8
Succession

Cortex-A57 (codename Atlas) is the successor to the Cortex-A15, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A57, which implemented the ARMv8 ISA, is the a performant core which is often combined with a number of lower power cores (e.g. Cortex-A53) in a big.LITTLE configuration to achieve better energy/performance.

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
Arm Compiler -mcpu=cortex-a57 -mtune=cortex-a57
GCC -mcpu=cortex-a57 -mtune=cortex-a57
LLVM -mcpu=cortex-a57 -mtune=cortex-a57

If the Cortex-A57 is coupled with the Cortex-A53 in a big.LITTLE system, GCC also supports the following option:

Compiler Tune
GCC -mtune=cortex-a57.cortex-a53

Architecture[edit]

Key changes from Cortex-A15[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Block Diagram[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Die[edit]

Cortex-A57 Clusters Silicon Areas (Estimated)
CompanySamsungRenesas
ChipExynos 5433R-Car H3
Process20 nm16 nm
Configuration4x Cortex-A57
+ 2 MiB L2		4x Cortex-A57
+ 2 MiB L2
Cluster Size~15.85 mm²~10.21 mm² cluster
Core Size~3 mm²~1.66 mm² cluster
Cache Size~3.87 mm²~3.28 mm² cluster

20 nm[edit]

Samsung Exynos 5433[edit]

  • Samsung 20 nm process
  • 113 mm² die size
  • Mali-T760 (6 EU)
  • Quad-core {Primary Cortex-A57 [Quad] + Secondary A53 [Quad]}
    • 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2
    • 4.4 mm² per cluster
      • ~1 mm² per core
      • ~0.55 mm² for 256 KiB L2 cache
  • Quad-core Cortex-A57 (big cores)
    • 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2
    • 15.85 mm² per cluster
      • ~3 mm² per core
      • ~3.87 mm² for 2 MiB L2 cache


exynos 5433 die.png

16 nm[edit]

Renesas R-Car H3[edit]

  • TSMC 16 nm process
  • 12.94 mm × 8.61 mm
  • 111.36 mm² die size
  • Quad-core Cortex-A53
    • ~3.27 mm² cluster
    • ~0.60 mm² core
    • ~0.7 mm² 512 KiB L2 cache
  • Quad-core Cortex-A57
    • ~10.21 mm² cluster
    • ~1.66 mm² core
    • ~3.28 mm² 2 MiB L2 cache
  • Cortex-R7 (dual-core lock-step)
    • ~1.04 mm² cluster
  • GX6650 GPU
    • ~28.12 mm²


r-car h3 die shot.png


A57 Cluster:

h3 a57 cluster.png

Bibliography[edit]

  • Pyo, Jungyul, et al. "23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015
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Facts about "Cortex-A57 - Microarchitectures - ARM"
RDF feed
codenameCortex-A57 +
designerARM Holdings +
first launchedOctober 30, 2012 +
full page namearm holdings/microarchitectures/cortex-a57 +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A57 +