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Difference between revisions of "risc-v/microarchitectures"
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| [[Andes]] || RV32IMAC || {{andes|N25|l=arch}} | | [[Andes]] || RV32IMAC || {{andes|N25|l=arch}} | ||
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− | | rowspan="3" | [[Codasip]] || | + | | rowspan="3" | [[Codasip]] || RV32[E,I]MC[F] || {{codasip|CODIX-BK3|l=arch}} |
|- | |- | ||
− | | | + | | RV[32,64]IMC[F][D] || {{codasip|CODIX-BK5|l=arch}} |
|- | |- | ||
− | | | + | | RV64IMAC, RV64GC || {{codasip|CODIX-BK7|l=arch}} |
|- | |- | ||
| [[Esperanto]] || RV64GC || {{esperanto|ET-Minion|l=arch}}, {{esperanto|ET-Maxion|l=arch}} | | [[Esperanto]] || RV64GC || {{esperanto|ET-Minion|l=arch}}, {{esperanto|ET-Maxion|l=arch}} |
Revision as of 04:48, 6 November 2020
RISC-V
Instruction Set Architecture
Instruction Set Architecture
General
Base Variants(base)
Standard Extensions(all)
Topics
- Foundation
- Non-Standard Extensions
- Addressing Modes
- Registers
- Assembly
- Interrupts
- Microarchitectures
Various microarchitectures have been designed for RISC-V by a number of companies. Below is a list of those microarchitectures.
List of RISC-V microarchitectures
Designer | ISA | Microarchitectures |
---|---|---|
Andes | RV32IMAC | N25 |
Codasip | RV32[E,I]MC[F] | CODIX-BK3 |
RV[32,64]IMC[F][D] | CODIX-BK5 | |
RV64IMAC, RV64GC | CODIX-BK7 | |
Esperanto | RV64GC | ET-Minion, ET-Maxion |
RV32IMC | BottleRocket | |
Microsemi | RV32IMA/F | Mi-V |
Nvidia | RV64I | NV-RISCV |
SiFive | RV32IMAC | E31 |
RV64IMAC | E51 | |
RV64GC | E54-MC | |
RV[32,64]IMAFDCV | 7 Series | |
T-Head | C910 | RV64GC[V,RV] |
E902 | RV32[EMC,EC,IMC] | |
Universities | RV32IM | Vanilla-5 |
RV32G/RV64G | Rocket |