Difference between revisions of "intel/xeon gold/5220r"

	Edit Values
	Xeon Gold 5220R
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	5220R
Market	Server
Introduction	February 24, 2020 (announced); February 24, 2020 (launched)
Release Price	$1,555.00 (tray); $1,561.00 (box)
Shop	Amazon
	General Specs
Family	Xeon Gold
Series	6200
Locked	Yes
Frequency	2,200 MHz
Turbo Frequency	4,000 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	22
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cascade Lake
Platform	Purley
Chipset	Lewisburg
Core Name	Cascade Lake R
Core Family	6
Core Model	85
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	24
Threads	48
Max Memory	1 TiB
	Multiprocessing
Max SMP	2-Way (Multiprocessor)
Interconnect	UPI
Interconnect Links	2
Interconnect Rate	10.4 GT/s
	Electrical
TDP	150 W
Tcase	0 °C – 86 °C
	Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647
	Succession
	Xeon Gold 5220

Revision as of 01:23, 28 February 2020

Xeon Gold 5220R is a 64-bit 24-core x86 high performance server microprocessor introduced by Intel in early 2020. The Gold 5220R is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 2-way multiprocessing, sports 2 AVX-512 FMA units as well as two Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 2.2 GHz with a TDP of 150 W and features a turbo boost frequency of up to 4.0 GHz.

Cache

Main article: Cascade Lake § Cache

The Xeon Gold 5220R features a larger non-default 35.75 MiB of L3, a size that would normally be found on a 26-core part.

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

1.5 MiB

1,536 KiB
1,572,864 B

L1I$	768 KiB 786,432 B 0.75 MiB	24x32 KiB	8-way set associative
L1D$	768 KiB 786,432 B 0.75 MiB	24x32 KiB	8-way set associative	write-back

L2$

24 MiB

24,576 KiB
25,165,824 B
0.0234 GiB

		24x1 MiB	16-way set associative	write-back

L3$

35.75 MiB

36,608 KiB
37,486,592 B
0.0349 GiB

		26x1.375 MiB	11-way set associative	write-back

Memory controller

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2666
Supports ECC	Yes
Max Mem	1 TiB
Controllers	2
Channels	6
Max Bandwidth	119.21 GiB/s 122,071.04 MiB/s 128.001 GB/s 128,000.763 MB/s 0.116 TiB/s 0.128 TB/s
Bandwidth	Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s

@@ Line 45: / Line 45: @@
 |predecessor link=intel/xeon_gold/5220
 }}
-'''Xeon Gold 5220R''' is a {{arch|64}} [[24-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2020]]. The Gold 5220R is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 2-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.2 GHz with a TDP of 150 W and features a {{intel|turbo boost}} frequency of up to 4.0 GHz.
+'''Xeon Gold 5220R''' is a {{arch|64}} [[24-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2020]]. The Gold 5220R is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 2-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 2.2 GHz with a TDP of 150 W and features a {{intel|turbo boost}} frequency of up to 4.0 GHz.
 == Cache ==
@@ Line 67: / Line 67: @@
 |l3 desc=11-way set associative
 |l3 policy=write-back
+}}
+== Memory controller ==
+{{memory controller
+|type=DDR4-2666
+|ecc=Yes
+|max mem=1 TiB
+|controllers=2
+|channels=6
+|max bandwidth=119.21 GiB/s
+|bandwidth schan=19.87 GiB/s
+|bandwidth dchan=39.74 GiB/s
+|bandwidth qchan=79.47 GiB/s
+|bandwidth hchan=119.21 GiB/s
 }}

base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	22 +
core count	24 +
core family	6 +
core model	85 +
core name	Cascade Lake R +
designer	Intel +
family	Xeon Gold +
first announced	February 24, 2020 +
first launched	February 24, 2020 +
full page name	intel/xeon gold/5220r +
has ecc memory support	true +
has locked clock multiplier	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description	8-way set associative +
l1d$ size	768 KiB (786,432 B, 0.75 MiB) +
l1i$ description	8-way set associative +
l1i$ size	768 KiB (786,432 B, 0.75 MiB) +
l2$ description	16-way set associative +
l2$ size	24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) +
l3$ description	11-way set associative +
l3$ size	35.75 MiB (36,608 KiB, 37,486,592 B, 0.0349 GiB) +
ldate	February 24, 2020 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	359.15 K (86 °C, 186.8 °F, 646.47 °R) +
max cpu count	2 +
max memory	1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
microarchitecture	Cascade Lake +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	5220R +
name	Xeon Gold 5220R +
package	FCLGA-3647 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 1,555.00 (€ 1,399.50, £ 1,259.55, ¥ 160,678.15) + and $ 1,561.00 (€ 1,404.90, £ 1,264.41, ¥ 161,298.13) +
release price (box)	$ 1,561.00 (€ 1,404.90, £ 1,264.41, ¥ 161,298.13) +
release price (tray)	$ 1,555.00 (€ 1,399.50, £ 1,259.55, ¥ 160,678.15) +
series	6200 +
smp interconnect	UPI +
smp interconnect links	2 +
smp interconnect rate	10.4 GT/s +
smp max ways	2 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2666 +
tdp	150 W (150,000 mW, 0.201 hp, 0.15 kW) +
technology	CMOS +
thread count	48 +
turbo frequency (1 core)	4,000 MHz (4 GHz, 4,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas

Samsung

Revision as of 01:23, 28 February 2020

Cache

Memory controller