Revision as of 01:19, 28 February 2020

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Xeon Gold 6242R
General Info
Designer	Intel
Manufacturer	Intel
Model Number	6242R
Market	Server
Introduction	February 24, 2020 (announced) February 24, 2020 (launched)
Release Price	$2,529.00 (tray)
Shop	Amazon
General Specs
Family	Xeon Gold
Series	6200
Locked	Yes
Frequency	3,100 MHz
Turbo Frequency	4,100 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	31
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cascade Lake
Platform	Purley
Chipset	Lewisburg
Core Name	Cascade Lake R
Core Family	6
Core Model	85
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	20
Threads	40
Max Memory	1 TiB
Multiprocessing
Max SMP	2-Way (Multiprocessor)
Interconnect	UPI
Interconnect Links	2
Interconnect Rate	10.4 GT/s
Electrical
TDP	205 W
Tcase	0 °C – 76 °C
Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647
Succession
Xeon Gold 6242

Xeon Gold 6242R is a 64-bit 20-core x86 high performance server microprocessor introduced by Intel in early 2020. The Gold 6242R is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 2-way multiprocessing, sports 2 AVX-512 FMA units as well as two Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.1 GHz with a TDP of 205 W and features a turbo boost frequency of up to 4.1 GHz.

Cache

Main article: Skylake § Cache

The Xeon Gold 6242R features a larger non-default 35.75 MiB of L3, a size that would normally be found on a 26-core part.

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 1.25 MiB 1,280 KiB 1,310,720 B L1I$ 640 KiB 655,360 B 0.625 MiB 20x32 KiB 8-way set associative   L1D$ 640 KiB 655,360 B 0.625 MiB 20x32 KiB 8-way set associative write-back L2$ 20 MiB 20,480 KiB 20,971,520 B 0.0195 GiB     20x1 MiB 16-way set associative write-back L3$ 35.75 MiB 36,608 KiB 37,486,592 B 0.0349 GiB     26x1.375 MiB 11-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2933 Supports ECC Yes Max Mem 1 TiB Controllers 2 Channels 6 Max Bandwidth 131.13 GiB/s 134,277.12 MiB/s 140.8 GB/s 140,799.765 MB/s 0.128 TiB/s 0.141 TB/s Bandwidth Single 21.86 GiB/s Double 43.71 GiB/s Quad 87.42 GiB/s Hexa 131.13 GiB/s