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'''Xeon Gold 6248R''' is a {{arch|64}} [[24-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2020]]. The Gold 6248R is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 2-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.0 GHz with a TDP of 205 W and features a {{intel|turbo boost}} frequency of up to 4.0 GHz.
 
'''Xeon Gold 6248R''' is a {{arch|64}} [[24-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2020]]. The Gold 6248R is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 2-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.0 GHz with a TDP of 205 W and features a {{intel|turbo boost}} frequency of up to 4.0 GHz.
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== Cache ==
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{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
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The Xeon Gold 6248R features a larger non-default 35.75 MiB of [[L3]], a size that would normally be found on a 26-core part.
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{{cache size
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|l1 cache=1.5 MiB
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|l1i cache=768 KiB
 +
|l1i break=24x32 KiB
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|l1i desc=8-way set associative
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|l1d cache=768 KiB
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|l1d break=24x32 KiB
 +
|l1d desc=8-way set associative
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|l1d policy=write-back
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|l2 cache=24 MiB
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|l2 break=24x1 MiB
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|l2 desc=16-way set associative
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|l2 policy=write-back
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|l3 cache=35.75 MiB
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|l3 break=26x1.375 MiB
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|l3 desc=11-way set associative
 +
|l3 policy=write-back
 +
}}

Revision as of 01:01, 28 February 2020

Edit Values
Xeon Gold 6248R
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number6248R
MarketServer
IntroductionFebruary 24, 2020 (announced)
February 24, 2020 (launched)
Release Price$2,700.00 (tray)
ShopAmazon
General Specs
FamilyXeon Gold
Series6200
LockedYes
Frequency3,000 MHz
Turbo Frequency4,000 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier30
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake R
Core Family6
Core Model85
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores24
Threads48
Max Memory1 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
InterconnectUPI
Interconnect Links2
Interconnect Rate10.4 GT/s
Electrical
TDP205 W
Tcase0 °C – 75 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Gold 6248R is a 64-bit 24-core x86 high performance server microprocessor introduced by Intel in early 2020. The Gold 6248R is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 2-way multiprocessing, sports 2 AVX-512 FMA units as well as two Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.0 GHz with a TDP of 205 W and features a turbo boost frequency of up to 4.0 GHz.

Cache

Main article: Cascade Lake § Cache

The Xeon Gold 6248R features a larger non-default 35.75 MiB of L3, a size that would normally be found on a 26-core part.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.5 MiB
1,536 KiB
1,572,864 B
L1I$768 KiB
786,432 B
0.75 MiB
24x32 KiB8-way set associative 
L1D$768 KiB
786,432 B
0.75 MiB
24x32 KiB8-way set associativewrite-back
L2$24 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
  24x1 MiB16-way set associativewrite-back
L3$35.75 MiB
36,608 KiB
37,486,592 B
0.0349 GiB
  26x1.375 MiB11-way set associativewrite-back
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/6248r&oldid=96178"
Facts about "Xeon Gold 6248R - Intel"
RDF feed
base frequency3,000 MHz (3 GHz, 3,000,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier30 +
core count24 +
core family6 +
core model85 +
core nameCascade Lake R +
designerIntel +
familyXeon Gold +
first announcedFebruary 24, 2020 +
first launchedFebruary 24, 2020 +
full page nameintel/xeon gold/6248r +
has locked clock multipliertrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
ldateFebruary 24, 2020 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max case temperature348.15 K (75 °C, 167 °F, 626.67 °R) +
max cpu count2 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
microarchitectureCascade Lake +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number6248R +
nameXeon Gold 6248R +
packageFCLGA-3647 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 2,700.00 (€ 2,430.00, £ 2,187.00, ¥ 278,991.00) +
release price (tray)$ 2,700.00 (€ 2,430.00, £ 2,187.00, ¥ 278,991.00) +
series6200 +
smp interconnectUPI +
smp interconnect links2 +
smp interconnect rate10.4 GT/s +
smp max ways2 +
socketSocket P + and LGA-3647 +
tdp205 W (205,000 mW, 0.275 hp, 0.205 kW) +
technologyCMOS +
thread count48 +
turbo frequency (1 core)4,000 MHz (4 GHz, 4,000,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +