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Difference between revisions of "arm holdings/microarchitectures/cortex-m55"
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'''Cortex-M55''' is an ultra-low-power [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for microcontrollers and embedded subsystems. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-M55, which implemented the {{arm|ARMv8.1-M}} ISA, is an ultra-low-power core which is often found in microcontrllers, low-power chips, and in the embedded subsystems of more powerful chips.
 
'''Cortex-M55''' is an ultra-low-power [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for microcontrollers and embedded subsystems. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-M55, which implemented the {{arm|ARMv8.1-M}} ISA, is an ultra-low-power core which is often found in microcontrllers, low-power chips, and in the embedded subsystems of more powerful chips.
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== History ==
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The Cortex-M55 was officially launched on February 10, 2020. Support for {{arm|custom instructions}} will be added in 2021.
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== Process Technology ==
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Though the Cortex-M55 is designed to be fabricated on various different [[process nodes]] ranging from very mature nodes such as the [[130 nm]] to leading-edge [[7 nm]] and [[5 nm]] nodes.
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== Compiler support ==
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{| class="wikitable"
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|-
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! Compiler !! Arch-Specific || Arch-Favorable
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|-
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| [[Arm Compiler]] || <code>-mcpu=cortex-m55</code> || <code>-mtune=cortex-m55</code>
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|-
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| [[GCC]] || <code>-mcpu=cortex-m55</code> || <code>-mtune=cortex-m55</code>
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|-
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| [[LLVM]] || <code>-march=cortex-m55</code> || <code>-mtune=cortex-m55</code>
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|}
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== Architecture ==
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== Block Diagram ===
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:[[File:cortex-m55 block diagram.svg|700px]]
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=== Memory Hierarchy ===
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The Cortex-M55 has a private L1I, L1D, I-TCM, and D-TCM. All four are configurable in size.
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* Cache
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** L1I Cache
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*** 0 - 64 KiB
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*** 2-way set associative
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*** Optional ECC support
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** L1D Cache
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*** 0 - 64 KiB
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*** 4-way set associative
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*** Supports both [[write-back]] (WB) and [[write-through]] (WT)
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*** Optional ECC support
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* [[tightly-coupled memory|TCM]]
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** I-TCM
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*** 0 - 16 MiB
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*** Supports wait-states
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*** Optional ECC support
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** D-TCM
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*** 0 - 16 MiB
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*** Supports wait-states
 +
*** Optional ECC support

Revision as of 00:42, 16 February 2020

Edit Values
Cortex-M55 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionFebruary 10, 2020
Process55 nm, 45 nm, 32 nm, 28 nm, 22 nm, 16 nm, 10 nm, 7 nm, 5 nm
Core Configs1, 2, 4
Pipeline
TypeScalar, Pipelined
OoOENo
SpeculativeNo
Reg RenamingNo
Stages4
Decode1-2-way
Instructions
ISAARMv8.1-M
ExtensionsFPU, Helium
Cache
L1I Cache0-64 KiB/core
2-way set associative
L1D Cache0-64 KiB/core
4-way set associative

Cortex-M55 is an ultra-low-power ARM microarchitecture designed by ARM Holdings for microcontrollers and embedded subsystems. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-M55, which implemented the ARMv8.1-M ISA, is an ultra-low-power core which is often found in microcontrllers, low-power chips, and in the embedded subsystems of more powerful chips.

History

The Cortex-M55 was officially launched on February 10, 2020. Support for custom instructions will be added in 2021.

Process Technology

Though the Cortex-M55 is designed to be fabricated on various different process nodes ranging from very mature nodes such as the 130 nm to leading-edge 7 nm and 5 nm nodes.

Compiler support

Compiler Arch-Specific Arch-Favorable
Arm Compiler -mcpu=cortex-m55 -mtune=cortex-m55
GCC -mcpu=cortex-m55 -mtune=cortex-m55
LLVM -march=cortex-m55 -mtune=cortex-m55

Architecture

Block Diagram =

cortex-m55 block diagram.svg

Memory Hierarchy

The Cortex-M55 has a private L1I, L1D, I-TCM, and D-TCM. All four are configurable in size.

  • Cache
    • L1I Cache
      • 0 - 64 KiB
      • 2-way set associative
      • Optional ECC support
    • L1D Cache
  • TCM
    • I-TCM
      • 0 - 16 MiB
      • Supports wait-states
      • Optional ECC support
    • D-TCM
      • 0 - 16 MiB
      • Supports wait-states
      • Optional ECC support
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Facts about "Cortex-M55 - Microarchitectures - ARM"
RDF feed
codenameCortex-M55 +
core count1 +, 2 + and 4 +
designerARM Holdings +
first launchedFebruary 10, 2020 +
full page namearm holdings/microarchitectures/cortex-m55 +
instance ofmicroarchitecture +
instruction set architectureARMv8.1-M +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-M55 +
pipeline stages4 +
process55 nm (0.055 μm, 5.5e-5 mm) +, 45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 22 nm (0.022 μm, 2.2e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) +