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Difference between revisions of "nervana/nnp/nnp-t 1400"
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|smp interconnect rate=28 GT/s
 
|smp interconnect rate=28 GT/s
 
|power=175 W
 
|power=175 W
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|tdp=375 W
 
|package name 1=intel,fcbga_3325
 
|package name 1=intel,fcbga_3325
 
}}
 
}}
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'''NNP-T 1400''' is a [[neural processor]] designed by [[Intel Nervana]] and introduced in late 2019. Fabricated on TSMC [[16 nm process]] based on the {{nervana|Spring Crest|l=arch}} microarchitecture, the NNP-T 1400 has the full 24 {{nervana|Spring Crest#Tensor Processing Cluster (TPC)|TPCs|l=arch}} enabled along with 60 MiB of scratchpad memory and operates at up to 1.1 GHz. This chip comes in an [[OPC OAM|OAM]] [[accelerator card]] form factor and incorporates 32 GiB of [[HBM2]] memory. This NPU exposes 16 {{nervana|Spring Crest#InterChip Link (ICL)|inter-chip links|l=arch}} for scale-out capabilities.
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'''NNP-T 1400''' is a [[training]] [[neural processor]] designed by [[Intel Nervana]] and introduced in late 2019. Fabricated on TSMC [[16 nm process]] based on the {{nervana|Spring Crest|l=arch}} microarchitecture, the NNP-T 1400 has the full 24 {{nervana|Spring Crest#Tensor Processing Cluster (TPC)|TPCs|l=arch}} enabled along with 60 MiB of scratchpad memory and operates at up to 1.1 GHz. This chip comes in an [[OPC OAM|OAM]] [[accelerator card]] form factor and incorporates 32 GiB of [[HBM2]] memory. This NPU exposes 16 {{nervana|Spring Crest#InterChip Link (ICL)|inter-chip links|l=arch}} for scale-out capabilities.
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[[File:spring crest mezzanine card (front).png|thumb|right|NNP-T 1300 [[OCP OAM|Mezzanine Card]].]]
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[[File:spring crest mezzanine card (front).png|thumb|right|NNP-T 1400 [[OCP OAM|Mezzanine Card]].]]
  
 
== Peak Performance ==
 
== Peak Performance ==
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The NNP-T 1400 comes in an [[OCP OAM]] mezzanine card  which enables support for various topologies including [[ring topology|ring]], [[hybrid cube mesh]], and [[fully connected]].
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The NNP-T 1400 has a peak performance of [[peak flops (half-precision)::108 TFLOPS]] ([[bfloat16]]).
  
 
== Cache ==
 
== Cache ==
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== Interconnect Topology ==
 
== Interconnect Topology ==
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The NNP-T 1300 comes in a dual-slot standard PCIe 4.0 card which enables support for only the ring topology. Chips are interconnected using the 16 available {{nervana|Spring Crest#InterChip Link (ICL)|inter-chip links|l=arch}}.
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The NNP-T 1400 comes in an [[OCP OAM]] mezzanine card which enables support for various topologies including [[ring topology|ring]], [[hybrid cube mesh]], and [[fully connected]].
  
 
== Die ==
 
== Die ==

Latest revision as of 09:51, 1 February 2020

Edit Values
NNP-T 1400
spring crest package (front).png
NPU with 4 HBM2 stacks
General Info
DesignerIntel
ManufacturerTSMC
Model NumberNNP-T 1400
MarketServer
IntroductionNovember 12, 2019 (announced)
November 12, 2019 (launched)
ShopAmazon
General Specs
FamilyNNP
SeriesNNP-T
Frequency1,100 MHz
Microarchitecture
MicroarchitectureSpring Crest
Process16 nm
Transistors27,000,000,000
TechnologyCMOS
Die680 mm²
Cores24
Max Memory32 GiB
Multiprocessing
InterconnectInterChip Link
Interconnect Links16
Interconnect Rate28 GT/s
Electrical
Power dissipation175 W
TDP375 W
Packaging
PackageFCBGA-3325 (FCBGA)
Dimension60 mm × 60 mm
Contacts3325
spring crest package (back).png

NNP-T 1400 is a training neural processor designed by Intel Nervana and introduced in late 2019. Fabricated on TSMC 16 nm process based on the Spring Crest microarchitecture, the NNP-T 1400 has the full 24 TPCs enabled along with 60 MiB of scratchpad memory and operates at up to 1.1 GHz. This chip comes in an OAM accelerator card form factor and incorporates 32 GiB of HBM2 memory. This NPU exposes 16 inter-chip links for scale-out capabilities.

NNP-T 1400 Mezzanine Card.

Peak Performance[edit]

The NNP-T 1400 has a peak performance of 108 TFLOPS
108,000,000,000,000 FLOPS
108,000,000,000 KFLOPS
108,000,000 MFLOPS
108,000 GFLOPS
0.108 PFLOPS
(bfloat16).

Cache[edit]

Main article: Spring Crest § Cache
  • 60 MiB of tightly-coupled scratchpad memory
    • 24 x 2.5 MiB/core

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeHBM2-2400
Supports ECCYes
Max Mem32 GiB
Controllers4
Channels32
Max Bandwidth1.2288 TB/s
1,144.409 GiB/s
1,171,875 MiB/s
1,228.8 GB/s
1,228,800 MB/s
1.118 TiB/s

Interconnect Topology[edit]

The NNP-T 1400 comes in an OCP OAM mezzanine card which enables support for various topologies including ring, hybrid cube mesh, and fully connected.

Die[edit]

Main article: Spring Crest § Die
  • 27,000,000,000 transistors
  • 680 mm² die size


spring crest floorplan.png

Product Brief[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=nervana/nnp/nnp-t_1400&oldid=95712"
Facts about "NNP-T 1400 - Intel Nervana"
RDF feed
back imageFile:spring crest package (back).png +
base frequency1,100 MHz (1.1 GHz, 1,100,000 kHz) +
core count24 +
designerIntel +
die area680 mm² (1.054 in², 6.8 cm², 680,000,000 µm²) +
familyNNP +
first announcedNovember 12, 2019 +
first launchedNovember 12, 2019 +
full page namenervana/nnp/nnp-t 1400 +
has ecc memory supporttrue +
instance ofmicroprocessor +
ldateNovember 12, 2019 +
main imageFile:spring crest package (front).png +
main image captionNPU with 4 HBM2 stacks +
manufacturerTSMC +
market segmentServer +
max memory32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB, 0.0313 TiB) +
max memory bandwidth1,144.409 GiB/s (1,171,875 MiB/s, 1,228.8 GB/s, 1,228,800 MB/s, 1.118 TiB/s, 1.229 TB/s) +
max memory channels32 +
microarchitectureSpring Crest +
model numberNNP-T 1400 +
nameNNP-T 1400 +
packageFCBGA-3325 +
peak flops (half-precision)108,000,000,000,000 FLOPS (108,000,000,000 KFLOPS, 108,000,000 MFLOPS, 108,000 GFLOPS, 108 TFLOPS, 0.108 PFLOPS, 1.08e-4 EFLOPS, 1.08e-7 ZFLOPS) +
power dissipation175 W (175,000 mW, 0.235 hp, 0.175 kW) +
process16 nm (0.016 μm, 1.6e-5 mm) +
seriesNNP-T +
smp interconnectInterChip Link +
smp interconnect links16 +
smp interconnect rate28 GT/s +
supported memory typeHBM2-2400 +
tdp375 W (375,000 mW, 0.503 hp, 0.375 kW) +
technologyCMOS +
transistor count27,000,000,000 +