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Difference between revisions of "intel/xeon gold/6154"
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{{intel title|Xeon Gold 6154}}
 
{{intel title|Xeon Gold 6154}}
−
{{mpu
+
{{chip
−
| future              = Yes
+
|name=Xeon Gold 6154
−
| name               = Xeon Gold 6154
+
|image=skylake sp (basic).png
−
| no image            = Yes
+
|designer=Intel
−
| image               =
+
|manufacturer=Intel
−
| image size          =
+
|model number=6154
−
| caption            =  
+
|part number=CD8067303592700
−
| designer           = Intel
+
|s-spec=SR3J5
−
| manufacturer       = Intel
+
|s-spec qs=QMQ9
−
| model number       = 6154
+
|market=Server
−
| part number         = CD8067303592700
+
|first announced=April 25, 2017
−
| part number 1      =
+
|first launched=July 11, 2017
−
| part number 2      =
+
|release price=$3,543.00
−
| s-spec             = SR3J5
+
|family=Xeon Gold
−
| s-spec 2            =  
+
|series=6100
−
| market             = Server
+
|locked=Yes
−
| first announced     = April 25, 2017
+
|frequency=3,000 MHz
−
| first launched     =  
+
|turbo frequency1=3,700 MHz
−
| last order          =  
+
|bus type=DMI 3.0
−
| last shipment      =  
+
|bus links=4
−
| release price      =  
+
|bus rate=8 GT/s
 +
|clock multiplier=30
 +
|cpuid=0x50654
 +
|isa=x86-64
 +
|isa family=x86
 +
|microarch=Skylake (server)
 +
|platform=Purley
 +
|chipset=Lewisburg
 +
|core name=Skylake SP
 +
|core family=6
 +
|core stepping=H0
 +
|process=14 nm
 +
|technology=CMOS
 +
|word size=64 bit
 +
|core count=18
 +
|thread count=36
 +
|max memory=768 GiB
 +
|max cpus=4
 +
|smp interconnect=UPI
 +
|smp interconnect links=3
 +
|smp interconnect rate=10.4 GT/s
 +
|tdp=200 W
 +
|tcase min=0 °C
 +
|tcase max=82 °C
 +
|dts min=0 °C
 +
|dts max=106 °C
 +
|package name 1=intel,fclga_3647
 +
|successor=Xeon Gold 6254
 +
|successor link=intel/xeon_gold/6254
 +
}}
 +
'''Xeon Gold 6154''' is a {{arch|64}} [[18-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6154, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3 GHz with a TDP of 200 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
  
−
| family              = Xeon Gold
+
== Cache ==
−
| series              = 6100
+
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
−
| locked              = Yes
+
{{cache size
−
| frequency          = 3.0 GHz
+
|l1 cache=1.125 MiB
−
| turbo frequency    =  
+
|l1i cache=576 KiB
−
| turbo frequency1    =  
+
|l1i break=18x32 KiB
−
| turbo frequency2    =  
+
|l1i desc=8-way set associative
−
| turbo frequency3    =  
+
|l1d cache=576 KiB
−
| turbo frequency4    =  
+
|l1d break=18x32 KiB
−
| turbo frequency5    =  
+
|l1d desc=8-way set associative
−
| turbo frequency6    =  
+
|l1d policy=write-back
−
| turbo frequency7    =  
+
|l2 cache=18 MiB
−
| turbo frequency8    =  
+
|l2 break=18x1 MiB
−
| bus type            = DMI 3.0
+
|l2 desc=16-way set associative
−
| bus speed          =  
+
|l2 policy=write-back
−
| bus rate            = 8 GT/s
+
|l3 cache=24.75 MiB
−
| bus links          = 4
+
|l3 break=18x1.375 MiB
−
| clock multiplier    = 30
+
|l3 desc=11-way set associative
−
| cpuid              =  
+
|l3 policy=write-back
−
| cpuid 2            =
+
}}
  
−
| isa family          = x86-64
+
== Memory controller ==
−
| isa                = x86
+
{{memory controller
−
| microarch          = Skylake
+
|type=DDR4-2666
−
| platform            = Purley
+
|ecc=Yes
−
| chipset            = Lewisburg
+
|max mem=768 GiB
−
| core name          = Skylake SP
+
|controllers=2
−
| core family        =  
+
|channels=6
−
| core model          =  
+
|max bandwidth=119.21 GiB/s
−
| core stepping      = H0
+
|bandwidth schan=19.87 GiB/s
−
| process            = 14 nm
+
|bandwidth dchan=39.74 GiB/s
−
| transistors        =  
+
|bandwidth qchan=79.47 GiB/s
−
| technology          = CMOS
+
|bandwidth hchan=119.21 GiB/s
−
| die area            = <!-- XX mm² -->
+
}}
−
| die width          =  
 
−
| die length          =  
 
−
| word size          = 64 bit
 
−
| core count          =
 
−
| thread count        =
 
−
| max cpus            = 4
 
−
| max memory          =
 
  
−
| electrical          =  
+
== Expansions ==
−
| power              =  
+
{{expansions
−
| average power      =  
+
| pcie revision     = 3.0
−
| idle power          =  
+
| pcie lanes         = 48
−
| v core              =
+
| pcie config       = x16
−
| v core tolerance    = <!-- OR ... -->
+
| pcie config 2      = x8
−
| v core min          =
+
| pcie config 3      = x4
−
| v core max          =
+
}}
−
| v io                =
 
−
| v io tolerance     =  
 
−
| v io 2              = <!-- OR ... -->
 
−
| v io 3              =
 
−
| sdp                =
 
−
| tdp                =
 
−
| tdp typical         =  
 
−
| ctdp down          =
 
−
| ctdp down frequency =
 
−
| ctdp up            =
 
−
| ctdp up frequency  =
 
−
| temp min            = <!-- use TJ/TC whenever possible instead -->
 
−
| temp max            =
 
−
| tjunc min          = <!-- .. °C -->
 
−
| tjunc max          =
 
−
| tcase min          =
 
−
| tcase max          =
 
−
| tstorage min       =  
 
−
| tstorage max        =  
 
−
| tambient min        =  
 
−
| tambient max        =
 
  
−
| package module 1    =  
+
== Features ==
−
| package module 2    =  
+
{{x86 features
−
<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
+
|real=Yes
−
| packaging          = Yes
+
|protected=Yes
−
| package 0          = FCLGA-3647
+
|smm=Yes
−
| package 0 type      = LGA
+
|fpu=Yes
−
| package 0 pins      = 3647
+
|x8616=Yes
−
| package 0 pitch    =  
+
|x8632=Yes
−
| package 0 width    =  
+
|x8664=Yes
−
| package 0 length    =  
+
|nx=Yes
−
| package 0 height    =  
+
|mmx=Yes
−
| socket 0            = LGA-3647
+
|emmx=Yes
−
| socket 0 type      = LGA
+
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=Yes
 +
|intelnodecontroller=Yes
 +
|intelnode=Yes
 +
|kpt=Yes
 +
|ptt=Yes
 +
|intelrunsure=Yes
 +
|mbe=Yes
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 
}}
 
}}
−
'''Xeon Gold 6154''' is a {{arch|64}} [[x86]] high-performance server [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6154 operates at 3.0 GHz
 
  
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=3,000 MHz
 +
|freq_1=3,700 MHz
 +
|freq_2=3,700 MHz
 +
|freq_3=3,700 MHz
 +
|freq_4=3,700 MHz
 +
|freq_5=3,700 MHz
 +
|freq_6=3,700 MHz
 +
|freq_7=3,700 MHz
 +
|freq_8=3,700 MHz
 +
|freq_9=3,700 MHz
 +
|freq_10=3,700 MHz
 +
|freq_11=3,700 MHz
 +
|freq_12=3,700 MHz
 +
|freq_13=3,700 MHz
 +
|freq_14=3,700 MHz
 +
|freq_15=3,700 MHz
 +
|freq_16=3,700 MHz
 +
|freq_17=3,700 MHz
 +
|freq_18=3,700 MHz
 +
|freq_avx2_base=2,600 MHz
 +
|freq_avx2_1=3,600 MHz
 +
|freq_avx2_2=3,600 MHz
 +
|freq_avx2_3=3,400 MHz
 +
|freq_avx2_4=3,400 MHz
 +
|freq_avx2_5=3,300 MHz
 +
|freq_avx2_6=3,300 MHz
 +
|freq_avx2_7=3,300 MHz
 +
|freq_avx2_8=3,300 MHz
 +
|freq_avx2_9=3,300 MHz
 +
|freq_avx2_10=3,300 MHz
 +
|freq_avx2_11=3,300 MHz
 +
|freq_avx2_12=3,300 MHz
 +
|freq_avx2_13=3,300 MHz
 +
|freq_avx2_14=3,300 MHz
 +
|freq_avx2_15=3,300 MHz
 +
|freq_avx2_16=3,300 MHz
 +
|freq_avx2_17=3,300 MHz
 +
|freq_avx2_18=3,300 MHz
 +
|freq_avx512_base=2,100 MHz
 +
|freq_avx512_1=3,500 MHz
 +
|freq_avx512_2=3,500 MHz
 +
|freq_avx512_3=3,300 MHz
 +
|freq_avx512_4=3,300 MHz
 +
|freq_avx512_5=3,200 MHz
 +
|freq_avx512_6=3,200 MHz
 +
|freq_avx512_7=3,200 MHz
 +
|freq_avx512_8=3,200 MHz
 +
|freq_avx512_9=3,100 MHz
 +
|freq_avx512_10=3,100 MHz
 +
|freq_avx512_11=3,100 MHz
 +
|freq_avx512_12=3,100 MHz
 +
|freq_avx512_13=2,800 MHz
 +
|freq_avx512_14=2,800 MHz
 +
|freq_avx512_15=2,800 MHz
 +
|freq_avx512_16=2,800 MHz
 +
|freq_avx512_17=2,700 MHz
 +
|freq_avx512_18=2,700 MHz
 +
}}
 +
 +
== Benchmarks ==
 +
{{benchmarks main
 +
|
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171003-00097.html|test_timestamp=2017-09-30 12:20:22-0400|chip_count=2|core_count=36|thread_count=36|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6154, 3.00GHz)|SPECspeed2017_int_base=8.92|SPECspeed2017_int_peak=9.16}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171003-00098.html|test_timestamp=2017-09-30 17:20:13-0400|chip_count=2|core_count=36|thread_count=36|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6154, 3.00GHz)|SPECspeed2017_fp_base=121|SPECspeed2017_fp_peak=122}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00129.html|test_timestamp=2017-10-11 07:31:37-0400|chip_count=2|core_count=36|thread_count=36|vendor=HPE|system=ProLiant DL380 Gen10 (3.00 GHz, Intel Xeon Gold 6154)|SPECspeed2017_fp_base=120|SPECspeed2017_fp_peak=}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00130.html|test_timestamp=2017-10-10 07:53:35-0400|chip_count=2|core_count=36|thread_count=36|vendor=HPE|system=ProLiant DL380 Gen10 (3.00 GHz, Intel Xeon Gold 6154)|SPECspeed2017_int_base=8.83|SPECspeed2017_int_peak=}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00134.html|test_timestamp=2017-10-11 13:56:41-0400|chip_count=2|core_count=36|copies_count=72|vendor=HPE|system=ProLiant DL380 Gen10 (3.00 GHz, Intel Xeon Gold 6154)|SPECrate2017_fp_base=198|SPECrate2017_fp_peak=}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00142.html|test_timestamp=2017-10-11 09:02:52-0400|chip_count=2|core_count=36|copies_count=72|vendor=HPE|system=ProLiant DL380 Gen10 (3.00 GHz, Intel Xeon Gold 6154)|SPECrate2017_int_base=213|SPECrate2017_int_peak=}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00314.html|test_timestamp=2017-10-26 14:43:55-0400|chip_count=2|core_count=36|thread_count=36|vendor=HPE|system=Synergy 480 Gen10 (3.00 GHz, Intel Xeon Gold 6154)|SPECspeed2017_int_base=8.75|SPECspeed2017_int_peak=}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00341.html|test_timestamp=2017-10-26 17:18:51-0400|chip_count=2|core_count=36|thread_count=36|vendor=HPE|system=Synergy 480 Gen10 (3.00 GHz, Intel Xeon Gold 6154)|SPECspeed2017_fp_base=119|SPECspeed2017_fp_peak=}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00425.html|test_timestamp=2017-10-26 01:03:45-0400|chip_count=2|core_count=36|copies_count=72|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6154, 3.00GHz)|SPECrate2017_fp_base=202|SPECrate2017_fp_peak=206}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00426.html|test_timestamp=2017-10-26 19:47:49-0400|chip_count=2|core_count=36|copies_count=72|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6154, 3.00GHz)|SPECrate2017_int_base=209|SPECrate2017_int_peak=221}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00427.html|test_timestamp=2017-10-27 06:32:11-0400|chip_count=2|core_count=36|thread_count=36|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6154, 3.00GHz)|SPECspeed2017_int_base=8.88|SPECspeed2017_int_peak=9.14}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00428.html|test_timestamp=2017-10-27 11:32:49-0400|chip_count=2|core_count=36|thread_count=36|vendor=Cisco Systems|system=Cisco UCS B200 M5 (Intel Xeon Gold 6154, 3.00GHz)|SPECspeed2017_fp_base=121|SPECspeed2017_fp_peak=122}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00458.html|test_timestamp=2017-10-25 11:16:42-0400|chip_count=2|core_count=36|copies_count=72|vendor=HPE|system=Synergy 480 Gen10 (3.00 GHz, Intel Xeon Gold 6154)|SPECrate2017_int_base=211|SPECrate2017_int_peak=}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00467.html|test_timestamp=2017-10-25 16:10:34-0400|chip_count=2|core_count=36|copies_count=72|vendor=HPE|system=Synergy 480 Gen10 (3.00 GHz, Intel Xeon Gold 6154)|SPECrate2017_fp_base=196|SPECrate2017_fp_peak=}}
 +
}}
  
−
{{unknown features}}
+
[[Category:microprocessor models by intel based on skylake extreme core count die]]

Latest revision as of 00:57, 29 December 2019

Edit Values
Xeon Gold 6154
skylake sp (basic).png
General Info
DesignerIntel
ManufacturerIntel
Model Number6154
Part NumberCD8067303592700
S-SpecSR3J5
QMQ9 (QS)
MarketServer
IntroductionApril 25, 2017 (announced)
July 11, 2017 (launched)
Release Price$3,543.00
ShopAmazon
General Specs
FamilyXeon Gold
Series6100
LockedYes
Frequency3,000 MHz
Turbo Frequency3,700 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier30
CPUID0x50654
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
PlatformPurley
ChipsetLewisburg
Core NameSkylake SP
Core Family6
Core SteppingH0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores18
Threads36
Max Memory768 GiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
InterconnectUPI
Interconnect Links3
Interconnect Rate10.4 GT/s
Electrical
TDP200 W
Tcase0 °C – 82 °C
TDTS0 °C – 106 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Gold 6154 is a 64-bit 18-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6154, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3 GHz with a TDP of 200 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.125 MiB
1,152 KiB
1,179,648 B
L1I$576 KiB
589,824 B
0.563 MiB
18x32 KiB8-way set associative 
L1D$576 KiB
589,824 B
0.563 MiB
18x32 KiB8-way set associativewrite-back
L2$18 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
  18x1 MiB16-way set associativewrite-back
L3$24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
  18x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem768 GiB
Controllers2
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
Node CtrlrNode Controller Support

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
123456789101112131415161718
Normal3,000 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz
AVX22,600 MHz3,600 MHz3,600 MHz3,400 MHz3,400 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz
AVX5122,100 MHz3,500 MHz3,500 MHz3,300 MHz3,300 MHz3,200 MHz3,200 MHz3,200 MHz3,200 MHz3,100 MHz3,100 MHz3,100 MHz3,100 MHz2,800 MHz2,800 MHz2,800 MHz2,800 MHz2,700 MHz2,700 MHz

Benchmarks[edit]

[Edit Benchmarks]

Test: SPEC CPU2017
Tested: 2017-09-30 12:20:22-0400
Chips: 2, Cores: 36, Threads: 36
benchmarks.svg
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6154, 3.00GHz)
SPECspeed2017_int_base: 8.92
SPECspeed2017_int_peak: 9.16
Test: SPEC CPU2017
Tested: 2017-09-30 17:20:13-0400
Chips: 2, Cores: 36, Threads: 36
benchmarks.svg
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6154, 3.00GHz)
SPECspeed2017_fp_base: 121
SPECspeed2017_fp_peak: 122
Test: SPEC CPU2017
Tested: 2017-10-11 07:31:37-0400
Chips: 2, Cores: 36, Threads: 36
benchmarks.svg
Vendor: HPE
System: ProLiant DL380 Gen10 (3.00 GHz, Intel Xeon Gold 6154)
SPECspeed2017_fp_base: 120
Test: SPEC CPU2017
Tested: 2017-10-10 07:53:35-0400
Chips: 2, Cores: 36, Threads: 36
benchmarks.svg
Vendor: HPE
System: ProLiant DL380 Gen10 (3.00 GHz, Intel Xeon Gold 6154)
SPECspeed2017_int_base: 8.83
Test: SPEC CPU2017
Tested: 2017-10-11 13:56:41-0400
Chips: 2, Cores: 36, Copies: 72
benchmarks.svg
Vendor: HPE
System: ProLiant DL380 Gen10 (3.00 GHz, Intel Xeon Gold 6154)
SPECrate2017_fp_base: 198
Test: SPEC CPU2017
Tested: 2017-10-11 09:02:52-0400
Chips: 2, Cores: 36, Copies: 72
benchmarks.svg
Vendor: HPE
System: ProLiant DL380 Gen10 (3.00 GHz, Intel Xeon Gold 6154)
SPECrate2017_int_base: 213
Test: SPEC CPU2017
Tested: 2017-10-26 14:43:55-0400
Chips: 2, Cores: 36, Threads: 36
benchmarks.svg
Vendor: HPE
System: Synergy 480 Gen10 (3.00 GHz, Intel Xeon Gold 6154)
SPECspeed2017_int_base: 8.75
Test: SPEC CPU2017
Tested: 2017-10-26 17:18:51-0400
Chips: 2, Cores: 36, Threads: 36
benchmarks.svg
Vendor: HPE
System: Synergy 480 Gen10 (3.00 GHz, Intel Xeon Gold 6154)
SPECspeed2017_fp_base: 119
Test: SPEC CPU2017
Tested: 2017-10-26 01:03:45-0400
Chips: 2, Cores: 36, Copies: 72
benchmarks.svg
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6154, 3.00GHz)
SPECrate2017_fp_base: 202
SPECrate2017_fp_peak: 206
Test: SPEC CPU2017
Tested: 2017-10-26 19:47:49-0400
Chips: 2, Cores: 36, Copies: 72
benchmarks.svg
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6154, 3.00GHz)
SPECrate2017_int_base: 209
SPECrate2017_int_peak: 221
Test: SPEC CPU2017
Tested: 2017-10-27 06:32:11-0400
Chips: 2, Cores: 36, Threads: 36
benchmarks.svg
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6154, 3.00GHz)
SPECspeed2017_int_base: 8.88
SPECspeed2017_int_peak: 9.14
Test: SPEC CPU2017
Tested: 2017-10-27 11:32:49-0400
Chips: 2, Cores: 36, Threads: 36
benchmarks.svg
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 6154, 3.00GHz)
SPECspeed2017_fp_base: 121
SPECspeed2017_fp_peak: 122
Test: SPEC CPU2017
Tested: 2017-10-25 11:16:42-0400
Chips: 2, Cores: 36, Copies: 72
benchmarks.svg
Vendor: HPE
System: Synergy 480 Gen10 (3.00 GHz, Intel Xeon Gold 6154)
SPECrate2017_int_base: 211
Test: SPEC CPU2017
Tested: 2017-10-25 16:10:34-0400
Chips: 2, Cores: 36, Copies: 72
benchmarks.svg
Vendor: HPE
System: Synergy 480 Gen10 (3.00 GHz, Intel Xeon Gold 6154)
SPECrate2017_fp_base: 196
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/6154&oldid=95151"
Facts about "Xeon Gold 6154 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 6154 - Intel#io +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel +, Xeon Gold 6154 - Intel + and Xeon Gold 6154 - Intel +
base frequency3,000 MHz (3 GHz, 3,000,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier30 +
core count18 +
core family6 +
core nameSkylake SP +
core steppingH0 +
cpuid0x50654 +
designerIntel +
familyXeon Gold +
first announcedApril 25, 2017 +
first launchedJuly 11, 2017 +
full page nameintel/xeon gold/6154 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size1,152 KiB (1,179,648 B, 1.125 MiB) +
l1d$ description8-way set associative +
l1d$ size576 KiB (589,824 B, 0.563 MiB) +
l1i$ description8-way set associative +
l1i$ size576 KiB (589,824 B, 0.563 MiB) +
l2$ description16-way set associative +
l2$ size18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) +
l3$ description11-way set associative +
l3$ size24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) +
ldateJuly 11, 2017 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer +
max case temperature355.15 K (82 °C, 179.6 °F, 639.27 °R) +
max cpu count4 +
max dts temperature106 °C +
max memory786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureSkylake (server) +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature0 °C +
model number6154 +
nameXeon Gold 6154 +
packageFCLGA-3647 +
part numberCD8067303592700 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 3,543.00 (€ 3,188.70, £ 2,869.83, ¥ 366,098.19) +
s-specSR3J5 +
s-spec (qs)QMQ9 +
series6100 +
smp interconnectUPI +
smp interconnect links3 +
smp interconnect rate10.4 GT/s +
smp max ways4 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2666 +
tdp200 W (200,000 mW, 0.268 hp, 0.2 kW) +
technologyCMOS +
thread count36 +
turbo frequency (1 core)3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +