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{{intel title|Xeon Gold 6126T}}
 
{{intel title|Xeon Gold 6126T}}
−
{{mpu
+
{{chip
−
| future              = Yes
+
|name=Xeon Gold 6126T
−
| name               = Xeon Gold 6126T
+
|image=skylake sp (basic).png
−
| no image            = Yes
+
|designer=Intel
−
| image              =
+
|manufacturer=Intel
−
| image size          =
+
|model number=6126T
−
| caption            =  
+
|part number=CD8067303593100
−
| designer           = Intel
+
|s-spec=SR3J9
−
| manufacturer       = Intel
+
|s-spec qs=QN39
−
| model number       = 6126T
+
|market=Server
−
| part number         = CD8067303593100
+
|first announced=April 25, 2017
−
| part number 1      =
+
|first launched=July 11, 2017
−
| part number 2      =
+
|release price=$1865.00
−
| s-spec             = SR3J9
+
|family=Xeon Gold
−
| s-spec 2            =  
+
|series=6100
−
| market             = Server
+
|locked=Yes
−
| first announced     = April 25, 2017
+
|frequency=2,600 MHz
−
| first launched     =  
+
|turbo frequency1=3,700 MHz
−
| last order          =  
+
|bus type=DMI 3.0
−
| last shipment      =  
+
|bus links=4
−
| release price      =  
+
|bus rate=8 GT/s
 +
|clock multiplier=26
 +
|cpuid=0x50654
 +
|isa=x86-64
 +
|isa family=x86
 +
|microarch=Skylake (server)
 +
|platform=Purley
 +
|chipset=Lewisburg
 +
|core name=Skylake SP
 +
|core family=6
 +
|core stepping=H0
 +
|process=14 nm
 +
|technology=CMOS
 +
|word size=64 bit
 +
|core count=12
 +
|thread count=24
 +
|max memory=768 GiB
 +
|max cpus=4
 +
|smp interconnect=UPI
 +
|smp interconnect links=3
 +
|smp interconnect rate=10.4 GT/s
 +
|tdp=125 W
 +
|tcase min=0 °C
 +
|tcase max=74 °C
 +
|package name 1=intel,fclga_3647
 +
}}
 +
'''Xeon Gold 6126T''' is a {{arch|64}} [[dodeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6126T, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.6 GHz with a TDP of 125 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
 +
 
 +
This specific model (''T'') has 10 years extended life guarantees designed to be [[NEBS]]-friendly for use in [[NEBS]]-complaint applications.
 +
 
 +
== Cache ==
 +
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
 +
The Xeon Gold 6126T features a considerably larger non-default 19.25 MiB of [[L3]], a size that would normally be found on a 14-core part.
 +
{{cache size
 +
|l1 cache=768 KiB
 +
|l1i cache=384 KiB
 +
|l1i break=12x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=384 KiB
 +
|l1d break=12x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=12 MiB
 +
|l2 break=12x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=19.25 MiB
 +
|l3 break=14x1.375 MiB
 +
|l3 desc=11-way set associative
 +
|l3 policy=write-back
 +
}}
  
−
| family              = Xeon Gold
+
== Memory controller ==
−
| series              = 6100
+
{{memory controller
−
| locked              = Yes
+
|type=DDR4-2666
−
| frequency          = 2.6 GHz
+
|ecc=Yes
−
| turbo frequency    =
+
|max mem=768 GiB
−
| turbo frequency1    =  
+
|controllers=2
−
| turbo frequency2    =  
+
|channels=6
−
| turbo frequency3    =  
+
|max bandwidth=119.21 GiB/s
−
| turbo frequency4    =  
+
|bandwidth schan=19.87 GiB/s
−
| turbo frequency5    =  
+
|bandwidth dchan=39.74 GiB/s
−
| turbo frequency6    =  
+
|bandwidth qchan=79.47 GiB/s
−
| turbo frequency7    =  
+
|bandwidth hchan=119.21 GiB/s
−
| turbo frequency8    =  
+
}}
−
| bus type            = DMI 3.0
 
−
| bus speed          =  
 
−
| bus rate            = 8 GT/s
 
−
| bus links          = 4
 
−
| clock multiplier    = 26
 
−
| cpuid              =
 
−
| cpuid 2            =
 
  
−
| isa family          = x86-64
+
== Expansions ==
−
| isa                = x86
+
{{expansions
−
| microarch          = Skylake
+
| pcie revision      = 3.0
−
| platform            = Purley
+
| pcie lanes         = 48
−
| chipset            = Lewisburg
+
| pcie config        = x16
−
| core name          = Skylake SP
+
| pcie config 2      = x8
−
| core family         =  
+
| pcie config 3      = x4
−
| core model          =  
+
}}
−
| core stepping      = H0
 
−
| process            = 14 nm
 
−
| transistors        =
 
−
| technology          = CMOS
 
−
| die area            = <!-- XX mm² -->
 
−
| die width          =
 
−
| die length          =
 
−
| word size          = 64 bit
 
−
| core count          =
 
−
| thread count        =
 
−
| max cpus            =
 
−
| max memory          =
 
  
−
| electrical          =  
+
== Features ==
−
| power              =  
+
{{x86 features
−
| average power      =  
+
|real=Yes
−
| idle power          =  
+
|protected=Yes
−
| v core              =  
+
|smm=Yes
−
| v core tolerance    = <!-- OR ... -->
+
|fpu=Yes
−
| v core min          =  
+
|x8616=Yes
−
| v core max          =  
+
|x8632=Yes
−
| v io                =  
+
|x8664=Yes
−
| v io tolerance      =  
+
|nx=Yes
−
| v io 2              = <!-- OR ... -->
+
|mmx=Yes
−
| v io 3              =  
+
|emmx=Yes
−
| sdp                =  
+
|sse=Yes
−
| tdp                =  
+
|sse2=Yes
−
| tdp typical        =  
+
|sse3=Yes
−
| ctdp down          =  
+
|ssse3=Yes
−
| ctdp down frequency =  
+
|sse41=Yes
−
| ctdp up            =  
+
|sse42=Yes
−
| ctdp up frequency  =  
+
|sse4a=No
−
| temp min            = <!-- use TJ/TC whenever possible instead -->
+
|avx=Yes
−
| temp max            =  
+
|avx2=Yes
−
| tjunc min          = <!-- .. °C -->
+
|avx512f=Yes
−
| tjunc max          =  
+
|avx512cd=Yes
−
| tcase min          =  
+
|avx512er=No
−
| tcase max          =  
+
|avx512pf=No
−
| tstorage min        =  
+
|avx512bw=Yes
−
| tstorage max        =  
+
|avx512dq=Yes
−
| tambient min        =  
+
|avx512vl=Yes
−
| tambient max        =  
+
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=Yes
 +
|intelnodecontroller=Yes
 +
|intelnode=Yes
 +
|kpt=Yes
 +
|ptt=Yes
 +
|intelrunsure=Yes
 +
|mbe=Yes
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
}}
  
−
| package module 1    =  
+
== Frequencies ==
−
| package module 2   =  
+
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
−
<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
+
{{frequency table
−
| packaging          = Yes
+
|freq_base=2,600 MHz
−
| package 0          = FCLGA-3647
+
|freq_1=3,700 MHz
−
| package 0 type      = LGA
+
|freq_2=3,700 MHz
−
| package 0 pins      = 3647
+
|freq_3=3,500 MHz
−
| package 0 pitch    =  
+
|freq_4=3,500 MHz
−
| package 0 width    =  
+
|freq_5=3,400 MHz
−
| package 0 length    =  
+
|freq_6=3,400 MHz
−
| package 0 height    =  
+
|freq_7=3,400 MHz
−
| socket 0            = LGA-3647
+
|freq_8=3,400 MHz
−
| socket 0 type      = LGA
+
|freq_9=3,300 MHz
 +
|freq_10=3,300 MHz
 +
|freq_11=3,300 MHz
 +
|freq_12=3,300 MHz
 +
|freq_avx2_base=2,200 MHz
 +
|freq_avx2_1=3,600 MHz
 +
|freq_avx2_2=3,600 MHz
 +
|freq_avx2_3=3,400 MHz
 +
|freq_avx2_4=3,400 MHz
 +
|freq_avx2_5=3,300 MHz
 +
|freq_avx2_6=3,300 MHz
 +
|freq_avx2_7=3,300 MHz
 +
|freq_avx2_8=3,300 MHz
 +
|freq_avx2_9=2,900 MHz
 +
|freq_avx2_10=2,900 MHz
 +
|freq_avx2_11=2,900 MHz
 +
|freq_avx2_12=2,900 MHz
 +
|freq_avx512_base=1,700 MHz
 +
|freq_avx512_1=3,500 MHz
 +
|freq_avx512_2=3,500 MHz
 +
|freq_avx512_3=3,300 MHz
 +
|freq_avx512_4=3,300 MHz
 +
|freq_avx512_5=2,600 MHz
 +
|freq_avx512_6=2,600 MHz
 +
|freq_avx512_7=2,600 MHz
 +
|freq_avx512_8=2,600 MHz
 +
|freq_avx512_9=2,300 MHz
 +
|freq_avx512_10=2,300 MHz
 +
|freq_avx512_11=2,300 MHz
 +
|freq_avx512_12=2,300 MHz
 
}}
 
}}
 +
 +
[[Category:microprocessor models by intel based on skylake extreme core count die]]

Latest revision as of 00:20, 29 December 2019

Edit Values
Xeon Gold 6126T
skylake sp (basic).png
General Info
DesignerIntel
ManufacturerIntel
Model Number6126T
Part NumberCD8067303593100
S-SpecSR3J9
QN39 (QS)
MarketServer
IntroductionApril 25, 2017 (announced)
July 11, 2017 (launched)
Release Price$1865.00
ShopAmazon
General Specs
FamilyXeon Gold
Series6100
LockedYes
Frequency2,600 MHz
Turbo Frequency3,700 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier26
CPUID0x50654
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
PlatformPurley
ChipsetLewisburg
Core NameSkylake SP
Core Family6
Core SteppingH0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores12
Threads24
Max Memory768 GiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
InterconnectUPI
Interconnect Links3
Interconnect Rate10.4 GT/s
Electrical
TDP125 W
Tcase0 °C – 74 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647

Xeon Gold 6126T is a 64-bit dodeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6126T, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.6 GHz with a TDP of 125 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

This specific model (T) has 10 years extended life guarantees designed to be NEBS-friendly for use in NEBS-complaint applications.

Cache[edit]

Main article: Skylake § Cache

The Xeon Gold 6126T features a considerably larger non-default 19.25 MiB of L3, a size that would normally be found on a 14-core part.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associative 
L1D$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associativewrite-back
L2$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  12x1 MiB16-way set associativewrite-back
L3$19.25 MiB
19,712 KiB
20,185,088 B
0.0188 GiB
  14x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem768 GiB
Controllers2
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
Node CtrlrNode Controller Support

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
123456789101112
Normal2,600 MHz3,700 MHz3,700 MHz3,500 MHz3,500 MHz3,400 MHz3,400 MHz3,400 MHz3,400 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz
AVX22,200 MHz3,600 MHz3,600 MHz3,400 MHz3,400 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz2,900 MHz2,900 MHz2,900 MHz2,900 MHz
AVX5121,700 MHz3,500 MHz3,500 MHz3,300 MHz3,300 MHz2,600 MHz2,600 MHz2,600 MHz2,600 MHz2,300 MHz2,300 MHz2,300 MHz2,300 MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/6126t&oldid=95129"
Facts about "Xeon Gold 6126T - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 6126T - Intel#io +
base frequency2,600 MHz (2.6 GHz, 2,600,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier26 +
core count12 +
core family6 +
core nameSkylake SP +
core steppingH0 +
cpuid0x50654 +
designerIntel +
familyXeon Gold +
first announcedApril 25, 2017 +
first launchedJuly 11, 2017 +
full page nameintel/xeon gold/6126t +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description16-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description11-way set associative +
l3$ size19.25 MiB (19,712 KiB, 20,185,088 B, 0.0188 GiB) +
ldateJuly 11, 2017 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer +
max case temperature347.15 K (74 °C, 165.2 °F, 624.87 °R) +
max cpu count4 +
max memory786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureSkylake (server) +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number6126T +
nameXeon Gold 6126T +
packageFCLGA-3647 +
part numberCD8067303593100 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 1,865.00 (€ 1,678.50, £ 1,510.65, ¥ 192,710.45) +
s-specSR3J9 +
s-spec (qs)QN39 +
series6100 +
smp interconnectUPI +
smp interconnect links3 +
smp interconnect rate10.4 GT/s +
smp max ways4 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2666 +
tdp125 W (125,000 mW, 0.168 hp, 0.125 kW) +
technologyCMOS +
thread count24 +
turbo frequency (1 core)3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +