Revision as of 04:56, 27 August 2019

Kirin 810 is a 64-bit octa-core mid-range performance mobile ARM SoC introduced by HiSilicon in mid-2019. This chip, which is fabricated on TSMC's 7 nm process, features two Cortex-A76 big cores operating at up to 2.27 GHz along with six Cortex-A55 little cores operating at up to 1.88 GHz. The 810 incorporates ARM's Mali-G52 MP6 GPU.

Cache

Main articles: Cortex-A55 § Cache and Cortex-A76 § Cache

For the Cortex-A76:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 2x64 KiB     L1D$ 128 KiB 131,072 B 0.125 MiB 2x64 KiB     L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     2x512 KiB

For the Cortex-A55:

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 384 KiB 393,216 B 0.375 MiB L1I$ 192 KiB 196,608 B 0.188 MiB 6x32 KiB     L1D$ 192 KiB 196,608 B 0.188 MiB 6x32 KiB     L2$ 768 KiB 0.75 MiB 786,432 B 7.324219e-4 GiB     6x128 KiB

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR4X-4266 Supports ECC No Max Mem 8 GiB Controllers 1 Channels 4 Width 16 bit Max Bandwidth 31.78 GiB/s 32,542.72 MiB/s 34.124 GB/s 34,123.515 MB/s 0.031 TiB/s 0.0341 TB/s Bandwidth Double 15.89 GiB/s Quad 31.78 GiB/s

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU Mali-G52 Designer ARM Holdings Execution Units 6 Max Displays 2 Frequency 850 MHz 0.85 GHz 850,000 KHz Max Resolution   2340x1080 Standards DirectX 12 OpenCL 2.0 OpenGL ES 3.2 OpenVG 1.1 Vulkan 1.0

• Hardware Acceleration
  • Decode: 1080p @ 60fps
  • Encode: 1080p @ 30fps

NPU

This is the first neural processing unit to use their own homegrown NPU based on Hisilicon's first generation Da Vinci architecture. The NPU contains one processor core and a scheduling core.

ISP

• 40 MP+ 24 MP dual

48 single

Wireless

• LTE Modem
  • DL: Up to User Equipment (UE) category 21
    • Downlink of up to 1.4 Gbps (4x4 MIMO + 256QAM 3CC CA = 1.2 Gbps, 2x2 MIMI + 256QAM + 1CC = 200 Mbps)
  • UL: Up to User Equipment (UE) category 18
    • Uplink of up to 200 Mbps (2x2 MIMO, 256-QAM, 1x20MHz CA)
• Wi-Fi 802.11 ac
• Bluetooth 5
• NFC
• GPS / A-GPS / GLONASS / BDS

Location

• GPS, AGPS, Glonass, Beidou

Utilizing devices

• Huawei Nova 5
• Huawai 9X Pro, 9X

This list is incomplete; you can help by expanding it.