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Difference between revisions of "intel/cores/cascade lake w"
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* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}})
 
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}})
 
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|TBT 2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Identity Protection}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|Volume Management Device}} (VMD).
 
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|TBT 2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Identity Protection}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|Volume Management Device}} (VMD).
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== Cascade Lake W Processors ==
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Note that for the lower [[core-count]]  models, the [[L3 cache]] size is larger than it would otherwise be due to additional cache slices being enabled from disabled [[physical core|cores]].
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{{future information}}
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          This table is generated automatically from the data in the actual articles.
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          If a microprocessor is missing from the list, an appropriate article for it needs to be
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          created and tagged accordingly.
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          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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{{comp table start}}
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<table class="comptable sortable tc4 tc5 tc11">
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{{comp table header|main|10:List of Cascade Lake W-based Processors}}
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{{comp table header|cols|Launched|Price|Cores|Threads|TDP|L2|L3|%Frequency|%Turbo|AVX-512 Units}}
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{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake W]]
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|?full page name
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|?model number
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|?first launched
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|?release price
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|?core count
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|?thread count
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|?tdp
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|?l2$ size
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|?l3$ size
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|?base frequency#GHz
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|?turbo frequency (1 core)#GHz
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|?number of avx-512 execution units
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|format=template
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|template=proc table 3
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|userparam=12
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|sort=model number
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|mainlabel=-
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}}
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{{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Cascade Lake W]]}}
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</table>
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{{comp table end}}
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== See also ==
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{{intel cascade lake core see also}}

Revision as of 11:43, 3 June 2019

Edit Values
Cascade Lake W
intel skylake w (front).png
General Info
DesignerIntel
ManufacturerIntel
Introduction2019 (announced)
2019 (launched)
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformGlacier Falls
Word Size
8 octets
16 nibbles
64 bit
Process14 nm
0.014 μm
1.4e-5 mm
Packaging
PackageFCLGA-2066 (LGA)
Dimension52.5 mm × 45 mm
Pitch1.016 mm
Contacts2066
SocketSocket R4
Succession

Cascade Lake W (Cascade Lake Workstations; CLS-W) is codename for Intel's enterprise workstation microprocessor line based on the Cascade Lake microarchitecture, succeeding Skylake W. Cascade Lake W processors feature a number of enhancements including a new AVX512 x86 extension for neural network / deep learning workloads, and introduces persistent memory support.

Overview

Cascade LAke W are enterprise workstation microprocessors. Those are a two-chip solution consisting of the microprocessor and the C422 chipset. All processors are socket Socket R4 (LGA-2066), manufactured on Intel's enhanced 14++ nm process based on the Skylake microarchitecture. Those are single-socket chips only. Geared toward business workstations, those processors come with all the related features such as vPro, Volume Management Device (VMD), and RAS.

Common Features

For the most part, Cascade Lake W processors come with all the features enabled and only core count and frequency being the differentiating feature. It's worth pointing out that the Skylake W come with AVX-512 along with two full execution units, similar to the high-end Skylake SP models (with the exception of the two low-end models). All models have 48 PCIe lanes and have all the following features in common:


Cascade Lake W Processors

Note that for the lower core-count models, the L3 cache size is larger than it would otherwise be due to additional cache slices being enabled from disabled cores.

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
 List of Cascade Lake W-based Processors
ModelLaunchedPriceCoresThreadsTDPL2L3FrequencyTurboAVX-512 Units
Count: 0

See also

arrow up 1.svgPower/Performance

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Facts about "Cascade Lake W - Cores - Intel"
RDF feed
designerIntel +
first announced2019 +
first launched2019 +
instance ofcore +
isax86-64 +
isa familyx86 +
main imageFile:intel skylake w (front).png +
manufacturerIntel +
microarchitectureCascade Lake +
nameCascade Lake W +
packageFCLGA-2066 +
platformGlacier Falls +
process14 nm (0.014 μm, 1.4e-5 mm) +
socketSocket R4 +
word size64 bit (8 octets, 16 nibbles) +