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Difference between revisions of "intel/microarchitectures/lakefield"
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{{intel title|Lakefield|arch}} | {{intel title|Lakefield|arch}} | ||
− | {{microarchitecture}} | + | {{microarchitecture |
+ | |atype=CPU | ||
+ | |name=Lakefield | ||
+ | |designer=Intel | ||
+ | |manufacturer=Intel | ||
+ | |introduction=2019 | ||
+ | |process=22 nm | ||
+ | |process 2=10 nm | ||
+ | |cores=5 | ||
+ | |type=Superscalar | ||
+ | |type 2=Superpipeline | ||
+ | |oooe=Yes | ||
+ | |speculative=Yes | ||
+ | |renaming=Yes | ||
+ | |isa=x86-64 | ||
+ | |l2=512 KiB + 1.5 MiB | ||
+ | |l3=4 MiB | ||
+ | |l3 per=chip | ||
+ | }} | ||
'''Lakefield''' ('''LKF''') is a high-performance low-power [[3d integrated circuit|3D]] microarchitecture designed by Intel and introduced in [[2019]]. | '''Lakefield''' ('''LKF''') is a high-performance low-power [[3d integrated circuit|3D]] microarchitecture designed by Intel and introduced in [[2019]]. |
Revision as of 09:46, 10 May 2019
Edit Values | |
Lakefield µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | 2019 |
Process | 22 nm, 10 nm |
Core Configs | 5 |
Pipeline | |
Type | Superscalar, Superpipeline |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Instructions | |
ISA | x86-64 |
Cache | |
L2 Cache | 512 KiB + 1.5 MiB |
L3 Cache | 4 MiB/chip |
Lakefield (LKF) is a high-performance low-power 3D microarchitecture designed by Intel and introduced in 2019.
Facts about "Lakefield - Microarchitectures - Intel"
codename | Lakefield + |
core count | 5 + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/lakefield + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Lakefield + |
process | 22 nm (0.022 μm, 2.2e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) + |