From WikiChip
Difference between revisions of "hisilicon/kunpeng/hi1616"
(6 intermediate revisions by the same user not shown) | |||
Line 1: | Line 1: | ||
− | {{hisilicon title|Hi1616}} | + | {{hisilicon title|Kunpeng 916 (Hi1616)}} |
{{chip | {{chip | ||
|name=Hi1616 | |name=Hi1616 | ||
Line 23: | Line 23: | ||
|max cpus=2 | |max cpus=2 | ||
|max memory=512 GiB | |max memory=512 GiB | ||
+ | |tdp=85 W | ||
}} | }} | ||
− | '''Hi1616''' is a [[dotriaconta-core]] {{arch|64}} [[ARM]] server microprocessor introduced by HiSilicon in mid-2017. Fabricated by [[TSMC]] on a [[16 nm process]], this chip incorporates 32 {{armh|Cortex-A72}} cores operating at 2.4 GHz. The Hi1616 supports up to 512 GiB of quad-channel DDR4-2400 memory. | + | [[File:hi1616 exhibit sign.jpg|thumb|right|Hi1616 display.]] |
+ | '''Kunpeng 916''' ('''Hi1616''') is a [[dotriaconta-core]] {{arch|64}} [[ARM]] server microprocessor introduced by HiSilicon in mid-2017. Fabricated by [[TSMC]] on a [[16 nm process]], this chip incorporates 32 {{armh|Cortex-A72}} cores operating at 2.4 GHz with a TDP of 85 W. The Hi1616 supports up to 512 GiB of quad-channel DDR4-2400 memory. This chip supports up to 2-way SMP with two ports supporting 96 Gb/s each. | ||
== Cache == | == Cache == | ||
Line 37: | Line 39: | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
|l2 cache=8 MiB | |l2 cache=8 MiB | ||
− | |l2 break= | + | |l2 break=8x1 MiB |
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
|l3 cache=32 MiB | |l3 cache=32 MiB | ||
Line 64: | Line 66: | ||
|type=PCIe | |type=PCIe | ||
|pcie revision=3.0 | |pcie revision=3.0 | ||
− | |pcie lanes= | + | |pcie lanes=46 |
− | |pcie config= | + | |pcie config=x16 |
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | }} | ||
+ | {{expansions entry | ||
+ | |type=USB | ||
+ | |usb revision=3.0 | ||
+ | |usb ports=2 | ||
+ | }} | ||
+ | {{expansions entry | ||
+ | |type=SATA | ||
+ | |sata revision=3.0 | ||
+ | |sata ports=8 | ||
}} | }} | ||
}} | }} | ||
Line 96: | Line 110: | ||
|rdm=No | |rdm=No | ||
}} | }} | ||
+ | |||
== Utilizing devices == | == Utilizing devices == | ||
* [[used by::HiSilicon D05]] | * [[used by::HiSilicon D05]] | ||
* [[used by::Huawei TaiShan 2280]] | * [[used by::Huawei TaiShan 2280]] | ||
− | + | ||
+ | <gallery widths=300px heights=200px> | ||
+ | File:hi1616 board 1.jpg | ||
+ | File:hi1616 board 2.jpg | ||
+ | File:hi1616 board 3.jpg | ||
+ | </gallery> |
Latest revision as of 09:12, 8 May 2019
Edit Values | |
Hi1616 | |
General Info | |
Designer | HiSilicon, ARM Holdings |
Manufacturer | TSMC |
Model Number | Hi1616 |
Market | Server |
Introduction | August, 2017 (announced) August, 2017 (launched) |
General Specs | |
Family | Hi16xx |
Frequency | 2,400 MHz |
Microarchitecture | |
ISA | ARMv8 (ARM) |
Microarchitecture | Cortex-A72 |
Core Name | Cortex-A72 |
Process | 16 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 32 |
Threads | 32 |
Max Memory | 512 GiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Electrical | |
TDP | 85 W |
Kunpeng 916 (Hi1616) is a dotriaconta-core 64-bit ARM server microprocessor introduced by HiSilicon in mid-2017. Fabricated by TSMC on a 16 nm process, this chip incorporates 32 Cortex-A72 cores operating at 2.4 GHz with a TDP of 85 W. The Hi1616 supports up to 512 GiB of quad-channel DDR4-2400 memory. This chip supports up to 2-way SMP with two ports supporting 96 Gb/s each.
Cache[edit]
- Main article: Cortex-A72 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller[edit]
Integrated Memory Controller
|
||||||||||||||||
|
Expansions[edit]
Expansion Options |
|||||||||||
|
Features[edit]
[Edit/Modify Supported Features]
Supported ARM Extensions & Processor Features
|
||||
|
Utilizing devices[edit]
- HiSilicon D05
- Huawei TaiShan 2280
Facts about "Kunpeng 916 (Hi1616) - HiSilicon"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Kunpeng 916 (Hi1616) - HiSilicon#pcie + |
base frequency | 2,400 MHz (2.4 GHz, 2,400,000 kHz) + |
core count | 32 + |
core name | Cortex-A72 + |
designer | HiSilicon + and ARM Holdings + |
family | Hi16xx + |
first announced | August 2017 + |
first launched | August 2017 + |
full page name | hisilicon/kunpeng/hi1616 + |
has ecc memory support | true + |
instance of | microprocessor + |
isa | ARMv8 + |
isa family | ARM + |
l1$ size | 2,560 KiB (2,621,440 B, 2.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) + |
ldate | August 2017 + |
main image | + |
manufacturer | TSMC + |
market segment | Server + |
max cpu count | 2 + |
max memory | 524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) + |
max memory bandwidth | 71.53 GiB/s (73,246.72 MiB/s, 76.805 GB/s, 76,804.753 MB/s, 0.0699 TiB/s, 0.0768 TB/s) + |
max memory channels | 4 + |
max sata ports | 8 + |
max usb ports | 2 + |
microarchitecture | Cortex-A72 + |
model number | Hi1616 + |
name | Hi1616 + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |
smp max ways | 2 + |
supported memory type | DDR4-2400 + |
tdp | 85 W (85,000 mW, 0.114 hp, 0.085 kW) + |
technology | CMOS + |
thread count | 32 + |
used by | HiSilicon D05 + and Huawei TaiShan 2280 + |
word size | 64 bit (8 octets, 16 nibbles) + |